摘要:
A data transmission apparatus which is connected with a shift register of a plural stages forming a forward path of data transmission line, and a shift register of a plural stages forming a backward path of the same, and a loop-back part therebetween, and comprises bypasses between the shift register on the forward path and on the backward path to bypass the transmitted data when significant data does not exist on the loop-back part side from a stage on which the bypass is comprised and no data stays at a stage where the bypass is comprised, so that data is transmitted at high speed, and which is constructed to be able to control the bypass from external, so that testing of circuitry is easy.
摘要:
A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.
摘要:
A data transmission apparatus for transmitting data between systems includes: an input data transmission path, an output data transmission path, and a branch data transmission path each constituted by a shift register, each data transmission path has a plurality of data storage circuits and a plurality of transfer control circuits each provided corresponding to each o--stage. The data storage circuit control a self stage data storage circuit in accordance with a control signal from the transfer control circuit of an adjacent stage. An initialization circuit for initializing the device is provided so that data on the data transmission path does not remain at the start of operation of the device.
摘要:
In a data flow machine, a program stored in advance is read out based on a tag included in a packet when the packet including first data is inputted from an external portion. Then, an instruction packet is formed by the content read out as a new tag and the first data, so that the instruction packet is outputted. Second data including the same tag as that included in the first data of the instruction packet read out from the program memory is detected. Firing processing is performed with respect to the first data and the second data as a pair and arithmetic processing is performed according to the instruction as a part of the tag included in an arithmetic packet, so that the arithmetic packet is outputted as a packet. The tag included in the packet is determined and the packet is outputted to an external portion or is inputted again to the internal portion.
摘要:
A data processing apparatus includes two data transmission paths formed likewise in a loop fashion. These data transmission paths include a plurality of latch registers connected in a cascade fashion respectively and are constituted as a so-called self-running type shift register wherein each data word constituting a data packet is shifted in sequence provided that a pre-stage register is vacant. Data packets are transmitted in the directions reverse to each other on the two loop-shaped data transmission paths an identification data included in each data packet being transmitted is detected in a section defined as a data packet pair detecting section. The detected identification data are compared in a comparing circuit and, one new data packet is produced from the two data packets in a manner that a data packet is joined from one data transmission path to the other data transmission path.
摘要:
A data transmission system comprises an input data transmission line (1), an output data transmission line (4), a branching data transmission line (5) and a jointing data transmission line (7) formed respectively by asynchronous free-running shift registers using a plurality of data latches (101 to 106, 401 & 402, 501 & 502, 701 & 702) and, C elements (111 to 116, 411 & 412, 511 & 512, 711 & 712) respectively. A branching control circuit 3 supplies data to be branched to the branching data transmission line (5) in response to the decision by a branching decision circuit (2) as to the fact that the data to be branched is transmitted on the input data transmission line (1). A jointing control circuit (6) supplies data to be joined to the output data transmission line (4) in response to the decision by an empty buffer verifier (8) as to the nonexistence of data in the input data transmission line (1) and the output data transmission line (4) when the data to be jointed is transmitted on the jointing data transmission line (7). Thus, the data transmission system has branching and jointing functions and if it is used as a constituent of a network, data can be transmitted among asynchronous systems.