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    Semiconductor package electrostatic discharge damage protection
    31.
    发明授权
    Semiconductor package electrostatic discharge damage protection 失效
    半导体封装静电放电损坏保护

    公开(公告)号：US5424896A

    公开(公告)日：1995-06-13

    申请号：US105833

    申请日：1993-08-12

    申请人： Nicholas F. Pasch ,  William Gascoyne

    发明人： Nicholas F. Pasch ,  William Gascoyne

    IPC分类号： H01L23/60 ,  H01T4/08 ,  H05K1/02 ,  H05K3/30 ,  H02H3/22

    CPC分类号： H01L23/60 ,  H01T4/08 ,  H05K1/026 ,  H01L2924/0002 ,  H05K2201/10689 ,  H05K2201/10787 ,  H05K3/308

    摘要： A semiconductor circuit package includes features forming an electrostatic charge distribution network having nodes which are defined by the electrical contact leads of the package for the semiconductor circuit, and which are effectively connected with one another by spark-gaps. In one embodiment electrical leads of the package are provided with pointed protrusions lying in the plane of the electrical leads. Accordingly, an inadvertent electrostatic discharge is distributed throughout the semiconductor circuit at safe voltage levels determined by the characteristics of the spark gaps of the charge distribution network.

    摘要翻译： 半导体电路封装包括形成静电电荷分布网络的特征，该静电电荷分布网络具有由用于半导体电路的封装的电接触引线限定的节点，并且通过火花间隙有效地彼此连接。 在一个实施例中，封装的电引线设置有位于电引线的平面中的尖突起。 因此，在由电荷分配网络的火花隙的特性确定的安全电压水平下，无意的静电放电分布在整个半导体电路中。

    Techniques for forming isolation structures
    34.
    发明授权
    Techniques for forming isolation structures 失效
    形成隔离结构的技术

    公开(公告)号：US5252503A

    公开(公告)日：1993-10-12

    申请号：US979305

    申请日：1992-11-20

    申请人： Nicholas F. Pasch

    发明人： Nicholas F. Pasch

    IPC分类号： H01L21/762 ,  H05K1/11 ,  H05K3/46 ,  H01L21/265

    CPC分类号： H01L21/7621 ,  H01L21/76227 ,  H05K1/115 ,  H05K3/4644 ,  Y10S148/135

    摘要： Various techniques of forming isolation structures between adjacent diffusion regions are disclosed. In one technique, a thermally-grown oxide isolation structure is gouged out, and subsequent poly extending into the gouged out isolation structure is substantially level with the diffusion region. In another technique, a trench (bathtub) is formed, lightly oxidized, overfilled with polysilicon or amorphous silicon, gouged out, and thermally treated to form a substantially planar isolation structure. In another technique, an isolation structure exhibiting bird's-heads and bird's-beaks is polished until the bird's-beaks are removed. Gouging of the diffusion area may be permitted to occur. A bipolar transistor structure can be formed in the gouged diffusion area, and will exhibit reduced spacing between the intrinsic base and collector without proportionally reduced spacing between the extrinsic base and the collector.

    摘要翻译： 公开了在相邻扩散区域之间形成隔离结构的各种技术。 在一种技术中，热生长的氧化物隔离结构被挖出，并且随后的扩展到被切掉的隔离结构中的多晶硅基本上与扩散区水平。 在另一种技术中，形成沟槽（浴缸），被轻微氧化，用多晶硅或非晶硅过度填充，凿出并热处理以形成基本上平面的隔离结构。 在另一种技术中，抛出展示鸟头和鸟喙的隔离结构，直到鸟的喙被去除。 可能允许发生扩散区的气泡。 可以在沟槽扩散区域中形成双极晶体管结构，并且将在本征基极和集电极之间表现出减小的间隔，而不会在外部基极和集电极之间成比例缩小的间隔。

    Method and apparatus for in-situ deformation of a surface, especially a non-planar optical surface
    35.
    发明授权
    Method and apparatus for in-situ deformation of a surface, especially a non-planar optical surface 失效
    用于表面，特别是非平面光学表面的原位变形的方法和装置

    公开(公告)号：US5247153A

    公开(公告)日：1993-09-21

    申请号：US711077

    申请日：1991-06-06

    申请人： Nicholas F. Pasch

    发明人： Nicholas F. Pasch

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70058 ,  G03F7/70241

    摘要： The surface of an optical element, such as the taking lens in semiconductor photolithographic apparatus, is deformed, in situ, by applying heat to the surface. A recipe for applying the heat to a selected area of the lens surface is developed by either measuring the image projected by the lens and comparing the measured image to the specified (mask) image, or by measuring the contour of the surface of the lens and comparing the measured contour to the lens' specified contour. The heat is applied by a laser, the output of which is focussed and scanned onto the surface of the lens. Method and apparatus are disclosed.

    摘要翻译： 光学元件的表面，例如半导体光刻设备中的拍摄镜头，通过向表面施加热而在原位变形。 通过测量透镜投射的图像并将测量的图像与指定的（掩模）图像进行比较，或者通过测量透镜的表面的轮廓，以及 将测得的轮廓与镜头的指定轮廓进行比较。 热量由激光器施加，其输出被聚焦并被扫描到透镜的表面上。 公开了方法和装置。

    Apparatus for isolation of flux materials in
    36.
    发明授权
    Apparatus for isolation of flux materials in "flip-chip" manufacturing 失效
    用于在“倒装芯片”制造中隔离焊剂材料的装置

    公开(公告)号：US5111279A

    公开(公告)日：1992-05-05

    申请号：US576182

    申请日：1990-08-30

    申请人： Nicholas F. Pasch ,  Vahak K. Sahakian ,  Conrad J. Dell'Oca

    发明人： Nicholas F. Pasch ,  Vahak K. Sahakian ,  Conrad J. Dell'Oca

    IPC分类号： G03F7/20 ,  H01L21/56 ,  H01L21/60 ,  H01L31/0232 ,  H05K3/30 ,  H05K3/34

    CPC分类号： G03F7/70433 ,  H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L31/0232 ,  H05K3/3436 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H05K2201/10424 ,  H05K2201/2036 ,  H05K2203/167 ,  H05K3/303 ,  H05K3/3431 ,  H05K3/3489 ,  Y02P70/613

    摘要： A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces. The core is formed of thermosetting organic resin, such as polyimide, or non-organic material such as alumina, polished sapphire, beryllium oxide, aluminum nitride or aluminum. The planar faces of the preformed planar structure are formed of thermoplastic resin or thermosetting material, such as polyacetal, epoxide resin or polystyrene. The preformed planar structure tends to draw the chip(s) together to the substrate, establishing a flip-chip structure of mechanical integrity. The preformed planar structure has a thickness of 5-50 microns, preferably on the order of 20-30 microns. Method and apparatus are disclosed.

    摘要翻译： 预成形的平面结构以倒装芯片结构插入在芯片和衬底之间，并且在芯片和衬底之间建立最小的间隙。 可以将液体通量施加到预形成的平面结构，以便将通量选择性地施加到芯片和基板上的焊球（垫）。 预成型的平面结构可以设置有与芯片和基板上的焊球对准的通孔。 在这种情况下，液体焊剂选择性地填充通孔，以在焊接期间输送到焊球。 通孔还有助于保持芯片和基板的配准。 通孔的尺寸可以确定当熔合在一起时由焊球形成的焊点的预定机械结构。 预成型的平面结构具有平面的芯和相对的平面。 芯由聚酰亚胺等热固性有机树脂，氧化铝，抛光蓝宝石，氧化铍，氮化铝，铝等非有机材料构成。 预成形的平面结构的平面由热塑性树脂或热固性材料如聚缩醛，环氧树脂或聚苯乙烯形成。 预制的平面结构倾向于将芯片一起拉到基板上，建立机械完整性的倒装芯片结构。 预成型的平面结构的厚度为5-50微米，优选为20-30微米。 公开了方法和装置。

    Forming a physical structure on an integrated circuit device and determining its size by measurement of resistance
    37.
    发明授权
    Forming a physical structure on an integrated circuit device and determining its size by measurement of resistance 失效
    在集成电路器件上形成物理结构，并通过测量电阻来确定其尺寸

    公开(公告)号：US5082792A

    公开(公告)日：1992-01-21

    申请号：US568269

    申请日：1990-08-15

    申请人： Nicholas F. Pasch ,  Philippe Schoenborn

    发明人： Nicholas F. Pasch ,  Philippe Schoenborn

    IPC分类号： G01R31/28 ,  H01L21/66

    CPC分类号： G01R31/2884 ,  H01L22/12 ,  Y10S148/162 ,  Y10S438/934

    摘要： A structure is formed on an electronic integrated circuit by altering the electrical characteristics of a diffused region of a substrate through a contact hole (window) in an insulating layer, in proportion to the size of said contact hole, such that the resistance of the diffused region is changed in a known and predictable fashion and may be measured electrically, giving indirect but accurate evidence of contact size in a completely nondestructive fashion. The measurements may be made on completed devices. Method and structure are disclosed.

    摘要翻译： 通过在绝缘层中与接触孔的尺寸成比例地改变绝缘层中的接触孔（窗口）来改变衬底的扩散区域的电特性，形成电子集成电路的结构，使得扩散的电阻 区域以已知和可预测的方式改变，并且可以电测量，以完全非破坏性的方式给出接触尺寸的间接但准确的证据。 测量可以在完成的设备上进行。 公开了方法和结构。

    Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level
    38.
    发明授权
    Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level 有权
    在至少局部互连级别和第一金属互连级别之间制造具有薄电介质的集成电路结构的工艺

    公开(公告)号：US06486056B2

    公开(公告)日：2002-11-26

    申请号：US09790821

    申请日：2001-02-22

    申请人： Nicholas F. Pasch ,  Rajat Rakkhit

    发明人： Nicholas F. Pasch ,  Rajat Rakkhit

    IPC分类号： H01L214763

    CPC分类号： H01L21/76895

    摘要： An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 Å, and preferably ranging from about 1000 Å to about 1500 Å. A first layer of metal interconnects is formed over the thin third dielectric layer. Conventionally formed filled contact openings extend from the substrate through the first dielectric layer to either filled vias or a local interconnect in the second dielectric layer. The metal interconnects are electrically connected to either filled vias or one or more local interconnects in the second dielectric layer by filled shallow vias in the thin third dielectric layer. The shallow vias in the thin third dielectric layer are preferably filled with the same metals used to form the first layer of metal interconnects.

    摘要翻译： 集成电路结构设置有局部互连层和第一金属互连层，其能够桥接在下面的导电区域上。 该结构包括形成为等于或优选地超过下层集成电路器件的最高导电区域的高度的高度或厚度的第一介电层; 形成在所述第一电介质层上的第二电介质层; 形成在第二介电层中的一个或多个局部互连; 以及形成在第二介质层上的薄的第三介电层和其中的局部互连。 薄的第三介电层的厚度不超过约2000埃，优选在约至约的范围内。 第一层金属互连形成在薄的第三介电层上。 常规形成的填充接触开口从衬底穿过第一介电层延伸到第二介电层中的填充通孔或局部互连。 金属互连通过薄第三介电层中的填充的浅通孔电连接到第二介电层中的填充通孔或一个或多个局部互连。 优选地，薄的第三电介质层中的浅通孔用用于形成第一金属互连层的金属填充相同的金属。

    Process for abrasive removal of copper from the back surface of a silicon substrate
    40.
    发明授权
    Process for abrasive removal of copper from the back surface of a silicon substrate 失效
    从硅衬底的背面去除铜的工艺

    公开(公告)号：US6059637A

    公开(公告)日：2000-05-09

    申请号：US990315

    申请日：1997-12-15

    申请人： Nicholas F. Pasch ,  Joe W. Zhao

    发明人： Nicholas F. Pasch ,  Joe W. Zhao

    IPC分类号： H01L21/304 ,  H01L21/321 ,  B24B1/00

    CPC分类号： H01L21/3212 ,  H01L21/304

    摘要： Described is an improvement in a process wherein integrated circuit structures are formed on a front surface of a silicon substrate and at least one layer of copper is deposited on the front surface of the substrate to form a layer of copper interconnects, and wherein at least some copper is also deposited on the back surface of the substrate during this deposition. The improvement comprises: prior to the end of the formation of the integrated circuit structures, abrasively removing, from the backside of the substrate, copper deposited thereon during the deposition of copper on the front surface. The step of abrasively removing copper from the back side of the substrate is preferably carried out before exposure of the substrate and the copper thereon, including copper deposited on the back side of the substrate, to any subsequent high temperature processing, and preferably, the step of abrasively removing the copper from the backside of the substrate comprises a chemical/mechanical polishing step which leaves a polished surface on the backside of the substrate to facilitate subsequent mounting or packaging of the integrated circuit structures.

    摘要翻译： 描述了在其中集成电路结构形成在硅衬底的前表面上并且至少一层铜沉积在衬底的前表面上以形成铜互连层的过程中的改进，并且其中至少一些 在该沉积期间，铜也沉积在衬底的背表面上。 该改进包括：在集成电路结构形成结束之前，在铜表面沉积期间，从衬底的背面去除铜沉积在其上。 从衬底的背面擦去铜的步骤优选在将衬底和其上的铜（其包括沉积在衬底的背面上的铜）暴露于任何随后的高温处理之前进行，优选地，步骤 从衬底的背面磨蚀性地去除铜的方法包括化学/机械抛光步骤，其在衬底的背面留下抛光表面，以便于后续的集成电路结构的安装或封装。