公开(公告)号：US07723824B2

公开(公告)日：2010-05-25

申请号：US11744621

申请日：2007-05-04

申请人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Fernando Guarin ,  J. Edwin Hostetter, Jr. ,  Stewart E. Rauch, III ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L29/73

CPC分类号： H01L29/7304 ,  H01L29/7378

摘要： A method for recovery of degradation caused by avalanche hot carriers is provided that includes subjecting an idle bipolar transistor exhibiting avalanche degradation to a thermal anneal step which increases temperature of the transistor thereby recovering the avalanche degradation of the bipolar transistor. In one embodiment, the annealing source is a self-heating structure that is a Si-containing resistor that is located side by side with an emitter of the bipolar transistor. During the recovering step, the bipolar transistor including the self-heating structure is placed in the idle mode (i.e., without bias) and a current from a separate circuit is flown through the self-heating structure. In another embodiment of the present, the annealing step is a result of providing a high forward current (around the peak fT current or greater) to the bipolar transistor while operating below the avalanche condition (VCB of less than 1 V). Under the above conditions, about 40% or greater of the degradation can be recovered. In yet another embodiment of the present invention, the thermal annealing step may include a rapid thermal anneal (RTA), a furnace anneal, a laser anneal or a spike anneal.

摘要翻译： 提供了一种用于回收由雪崩热载体引起的降解的方法，其包括使表现出雪崩降解的空闲双极晶体管经历热退火步骤，所述热退火步骤增加了晶体管的温度，从而恢复了双极晶体管的雪崩劣化。 在一个实施例中，退火源是自发热结构，其是与双极晶体管的发射极并排放置的含Si电阻器。 在恢复步骤期间，包括自发热结构的双极晶体管被置于空闲模式（即，没有偏压），并且来自单独电路的电流流过自热结构。 在本发明的另一个实施例中，退火步骤是在低于雪崩条件（VCB小于1V）的情况下向双极晶体管提供高正向电流（围绕峰值fT电流或更大）的结果。 在上述条件下，可以回收约40％以上的降解。 在本发明的又一实施例中，热退火步骤可以包括快速热退火（RTA），炉退火，激光退火或尖峰退火。

公开(公告)号：US07683651B2

公开(公告)日：2010-03-23

申请号：US12348434

申请日：2009-01-05

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang

IPC分类号： G01R31/26 ,  G01R19/00 ,  H01L23/58

CPC分类号： G01R31/2858

摘要： A test structure for electromigration and related method are disclosed. The test structure may include an array of a plurality of multilink test sets, each multilink test set including a plurality of metal lines positioned within a dielectric material and connected in a serial configuration; each multilink test set being connected in a parallel configuration with the other multilink test sets, the parallel configuration including a first electrical connection to a cathode end of a first metal line in each multilink test set and a second electrical connection to an anode end of a last metal line in each multilink test set.

摘要翻译： 公开了用于电迁移的测试结构及相关方法。 测试结构可以包括多个多链测试集的阵列，每个多链测试集包括定位在电介质材料内并以串联配置连接的多个金属线; 每个多链路测试集合以与其他多链路测试集合的并行配置连接，所述并行配置包括到每个多链路测试集合中的第一金属线的阴极端的第一电连接和到第一金属线的阳极端的第二电连接 每条多链测试集中的最后一条金属线。

公开(公告)号：US07671444B2

公开(公告)日：2010-03-02

申请号：US11767580

申请日：2007-06-25

申请人： Ping-Chuan Wang ,  Wai-Kin Li

发明人： Ping-Chuan Wang ,  Wai-Kin Li

IPC分类号： H01L23/525 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.

摘要翻译： 本公开总体上涉及集成电路（IC）芯片制造，更具体地，涉及包括开口，层间电介质中的第一通孔和第二通孔的电熔丝装置，其中开口，第一通孔和第二通孔 连接到层间电介质下面的互连; 包围第一通孔和第二通孔的电介质层; 以及在所述介电层上的金属层，其中所述金属层用金属填充所述开口，并且其中所述第一通孔和所述第二通孔基本为空，以允许在所述电熔丝装置的重新编程期间所述互连件的电迁移。

公开(公告)号：US20090200598A1

公开(公告)日：2009-08-13

申请号：US12027496

申请日：2008-02-07

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

公开(公告)号：US20090106726A1

公开(公告)日：2009-04-23

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20090072406A1

公开(公告)日：2009-03-19

申请号：US11856970

申请日：2007-09-18

申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Kaushik Chanda

发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Kaushik Chanda

IPC分类号： H01L21/31

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer does not form an alloy with an underlying conductive material that is embedded within the first dielectric material. In some embodiments of the present invention, the metallic interfacial layer is also present on exposed sidewalls of the second dielectric material that is located atop the first dielectric material. Atop the metallic interfacial layer there is present a diffusion barrier liner. In some embodiments, the diffusion barrier liner includes a lower layer of a metallic nitride and an upper layer of a metal. In accordance with the present invention, the metallic interfacial layer also does not form an alloy with any portion of the diffusion barrier liner.

摘要翻译： 提供了一种互连结构，其中在不引入互连结构内的气蚀特征的情况下，其电迁移阻力得到改善。 互连结构包括金属界面层，其至少水平存在于位于第二介电材料内的开口的底部，该第二电介质材料位于第一电介质材料的顶部，该第一介电材料包括嵌入其中的第一导电材料。 金属界面层不与嵌入在第一介电材料内的下面的导电材料形成合金。 在本发明的一些实施例中，金属界面层也存在于位于第一介电材料顶部的第二介电材料的暴露的侧壁上。 在金属界面层顶部存在扩散阻挡层。 在一些实施例中，扩散阻挡衬里包括金属氮化物的下层和金属的上层。 根据本发明，金属界面层也不与扩散阻挡衬里的任何部分形成合金。

公开(公告)号：US20080308942A1

公开(公告)日：2008-12-18

申请号：US11761495

申请日：2007-06-12

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76865 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

摘要翻译： 包括其中具有金属布线的电介质层，从金属布线向下延伸的孔，在金属布线上方的金属盖层和位于金属盖层的一部分内的局部电介质盖的半导体布线结构 公开了与金属布线的接触和相关方法。 局部电介质盖表示在双镶嵌互连的金属布线中有意创造的弱点，其在管线中引起电迁移（EM）空隙，而不是在从金属布线向下延伸的通孔的底部。 由于线路中的临界空隙尺寸失效，特别是金属盖层（衬垫）冗余度，远远大于通孔失效，所以EM寿命可以显着提高。

公开(公告)号：US20080254624A1

公开(公告)日：2008-10-16

申请号：US11734958

申请日：2007-04-13

申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76849

摘要： A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap.

摘要翻译： 描述了形成用于互连结构的改进的金属帽的结构和方法。 该方法包括在第一绝缘层的上部形成互连特征; 在所述互连特征和所述第一绝缘层上方覆盖介电覆盖层; 在所述电介质覆盖层上沉积第二绝缘层; 蚀刻所述第二绝缘层的一部分以形成通孔开口，其中所述通孔开口暴露所述互连特征的一部分; 轰击互连特征的部分以在互连特征的一部分中定义测量特征; 蚀刻通孔测量特征，用于形成邻近互连特征和电介质覆盖层的底切区域; 沉积贵金属层，所述贵金属层填充通孔测量特征的底切区域以形成金属盖; 以及在所述金属盖上沉积金属层。

公开(公告)号：US20080128907A1

公开(公告)日：2008-06-05

申请号：US11565810

申请日：2006-12-01

申请人： Chih-Chao Yang ,  Ping-Chuan Wang

发明人： Chih-Chao Yang ,  Ping-Chuan Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods of making the same. The semiconductor structure includes an interconnect feature substantially filled with a conductive material and disposed within a first dielectric material, and a second dielectric material comprising a contact via over the interconnect feature. The semiconductor structure further includes a gouging feature in the conductive material and adjacent to the contact via, and a first liner material deposited substantially only on surfaces of the conductive material in the gouging feature.

摘要翻译： 半导体结构及其制作方法。 半导体结构包括基本上填充有导电材料并且设置在第一电介质材料内的互连特征，以及包括互连特征上的接触通孔的第二电介质材料。 半导体结构还包括在导电材料中并且邻近接触通孔的气泡特征，以及基本上仅在气刨特征中的导电材料的表面上沉积的第一衬里材料。

公开(公告)号：US20080122096A1

公开(公告)日：2008-05-29

申请号：US11460314

申请日：2006-07-27

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。