摘要:
Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.
摘要:
A polymer memory system stores digital data in dipole moments of polymer memory cells. Apparatus is disclosed having polymer memory cells provided within an LCD display chamber. Embodiments provide for a high degree of integration the polymer memory system and a display system by providing polymer memory cells within the chamber. The memory cells may be located in non-viewable regions of the chamber. Thus, the memory cells provide only limited interference with the image-bearing functions of the display (if they interfere at all) but provide an extra dimension of functionality to the display.
摘要:
A method of optimizing a data path in a multi-port bridge for a local area network (LAN) includes steps of: identifying a data path through the multi-port bridge wherein the data path includes a plurality of stages in a serial arrangement, wherein each stage performs a corresponding operation on data received from the LAN by the multi-port bridge; identifying a stage in the data path wherein the identified stage requires a period of time to perform its corresponding operation which is longer than any other stage; and subdividing the identified stage into two or more subdivided stages wherein the operations performed by the subdivided stages collectively perform the operation associated with the identified stage and wherein each of the two or more subdivided stages requires a period of time to perform its corresponding operation which is shorter than the period of time required for the identified stage to perform its corresponding operation. The method can include determining a bandwidth required for the multi-port bridge; and determining a frequency for a clock signal based upon the bandwidth. The method can also include repeatedly subdividing selected stages until a slowest stage in the data path is operable according to the clock signal. The invention results in a beneficial trade-off in which bandwidth for the multi-port bridge and latency are both increased.
摘要:
Merchants create ecommerce-enabled ad units advertising items offered by the merchants. The ad units contain functionality enabling customers to purchase the items by interacting with the ad units. The ad units have associated bid prices that the merchants agree to pay for sales through the ad units. The merchants provide the ad units to a broker. The broker publishes the ad units on web pages provided by publishers. A customer receiving a web page interacts with the ad unit to purchase the item. During the interactions, the broker dynamically updates the ad unit to carry out the transaction. The broker collects the bid price from the merchant and shares it with the publisher that published the page on which the ad unit appeared.
摘要:
Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.
摘要:
Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.
摘要:
Merchants create ecommerce-enabled ad units advertising items offered by the merchants. The ad units contain functionality enabling customers to purchase the items by interacting with the ad units. The ad units have associated bid prices that the merchants agree to pay for sales through the ad units. The merchants provide the ad units to a broker. The broker publishes the ad units on web pages provided by publishers as comparison shop ad units that contain multiple ad units and functionality for navigating among them. A customer receiving a web page interacts with an ad unit to purchase the item. During the interactions, the broker dynamically updates the ad unit to conduct the transaction.
摘要:
Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.
摘要:
The invention relates to novel air barriers made from elastomeric compositions. In particular, the invention relates to novel air barriers such as innerliners, air sleeves, and innertubes made from novel C4 to C7 isoolefin based polymers with new sequence distributions or that are substantially free of long chain branching.
摘要翻译:本发明涉及由弹性体组合物制成的新型空气屏障。 特别地,本发明涉及新颖的空气屏障,例如由具有新的序列分布的新C C 4→C 7 N 6异构烯烃基聚合物制成的内衬,空气套管和内管,或者 基本上不含长链支化。
摘要:
Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.