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    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device
    31.
    发明授权
    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
    在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法

    公开(公告)号：US07656742B2

    公开(公告)日：2010-02-02

    申请号：US12128464

    申请日：2008-05-28

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    IPC分类号： G11C8/00

    CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

    摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

    摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

    Small swing signal receiver for low power consumption and semiconductor device including the same
    32.
    发明授权
    Small swing signal receiver for low power consumption and semiconductor device including the same 有权
    用于低功耗的小型摆动信号接收器和包括它的半导体器件

    公开(公告)号：US07463072B2

    公开(公告)日：2008-12-09

    申请号：US11566651

    申请日：2006-12-04

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Woo-Jin Lee

    IPC分类号： H03B1/00

    CPC分类号： H03K19/0013 ,  H03K19/018521

    摘要： A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

    摘要翻译： 一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。

    Data output buffer and memory device
    34.
    发明授权
    Data output buffer and memory device 有权
    数据输出缓冲器和存储器件

    公开(公告)号：US08553471B2

    公开(公告)日：2013-10-08

    申请号：US13239478

    申请日：2011-09-22

    申请人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    发明人： Si-Hong Kim ,  Seung-Jun Bae ,  Jin-Il Lee ,  Kwang-Il Park

    IPC分类号： G11C7/10 ,  G11C7/00

    CPC分类号： G11C7/1057 ,  G11C29/022 ,  G11C29/028 ,  G11C2207/2254

    摘要： A data output buffer includes a driving unit and a control unit. The driving unit selectively performs a termination operation that provides a termination impedance to a transmission line coupled to an external pin, and a driving operation that provides a drive impedance to the transmission line while outputting read data. The control unit adjusts a value of the termination impedance and a value of the drive impedance based on an output voltage at the external pin during a termination mode, and controls the driving unit to selectively perform one of the termination operation and the driving operation during a driving mode.

    摘要翻译： 数据输出缓冲器包括驱动单元和控制单元。 驱动单元选择性地执行向耦合到外部引脚的传输线提供终止阻抗的终止操作，以及在输出读取数据的同时向传输线提供驱动阻抗的驱动操作。 控制单元在终端模式期间根据外部引脚的输出电压来调整终端阻抗的值和驱动阻抗的值，并且控制驱动单元选择性地执行终止操作和驱动操作之一 驾驶模式。

    Data write training method and semiconductor device performing the same
    35.
    发明授权
    Data write training method and semiconductor device performing the same 有权
    数据写入训练方法和执行相同的半导体器件

    公开(公告)号：US08437216B2

    公开(公告)日：2013-05-07

    申请号：US13270710

    申请日：2011-10-11

    申请人： Tae-Young Oh ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    发明人： Tae-Young Oh ,  Young-Soo Sohn ,  Seung-Jun Bae ,  Kwang-Il Park

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1087 ,  G11C7/1093 ,  G11C2207/2254

    摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.

    摘要翻译： 实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据 数据线。 在不附加训练命令的情况下执行发送第一写入数据。

    Memory system, memory device, and output data strobe signal generating method
    36.
    发明授权
    Memory system, memory device, and output data strobe signal generating method 失效
    存储器系统，存储器件和输出数据选通信号生成方法

    公开(公告)号：US07733715B2

    公开(公告)日：2010-06-08

    申请号：US12071347

    申请日：2008-02-20

    申请人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

    发明人： Kwang-Il Park ,  Seong-Jin Jang ,  Ho-Young Song

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

    摘要： An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

    摘要翻译： 输出数据选通信号产生方法和包括多个半导体存储器件的存储器系统以及用于控制半导体存储器件的存储器控​​制器，其中存储器控制器向半导体存储器件提供命令信号和片选信号。 一个或多个半导体存储器件可以响应于命令信号和芯片选择信号来检测读取命令和伪读取命令，并且基于所计算的前导码周期数生成一个或多个前导码信号。

    Semiconductor memory device and latency signal generating method thereof
    37.
    发明申请
    Semiconductor memory device and latency signal generating method thereof 有权
    半导体存储器件及其等待时间信号产生方法

    公开(公告)号：US20080291753A1

    公开(公告)日：2008-11-27

    申请号：US12219816

    申请日：2008-07-29

    申请人： Kwang-Il Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

    发明人： Kwang-Il Park ,  Young-Hyun Jun ,  Seong-Jin Jang ,  Ho-Young Song

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

    摘要： A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

    摘要翻译： 公开了等待信号产生方法和相应的半导体存储器件。 这种方法包括：接收半导体存储器件的时钟信号; 接收模式表征信号; 提供DQS; 以及根据模式表征信号调整DQS的前导码状态的持续时间，以促进DQS的选通状态与时钟信号的一致性。

    Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device
    39.
    发明授权
    Semiconductor device capable of controlling OCD and ODT circuits and control method used by the semiconductor device 有权
    能够控制OCD和ODT电路的半导体器件和半导体器件使用的控制方法

    公开(公告)号：US07420387B2

    公开(公告)日：2008-09-02

    申请号：US11402123

    申请日：2006-04-11

    申请人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

    发明人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

    IPC分类号： H03K17/16

    CPC分类号： H03K19/0005

    摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

    摘要翻译： 提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。 半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗 根据调整后的控制代码进行调整。 半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。 因此，可以更精确地调整OCD电路或ODT电路的阻抗。

    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device
    40.
    发明授权
    Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
    在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法

    公开(公告)号：US07394720B2

    公开(公告)日：2008-07-01

    申请号：US11560746

    申请日：2006-11-16

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Jeong-Don Lim ,  Kwang-Il Park ,  Ho-Young Song ,  Woo-Jin Lee

    IPC分类号： G11C8/00

    CPC分类号： G06F12/02 ,  G11C7/1078 ,  G11C7/109

    摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

    摘要翻译： 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。