公开(公告)号：US10324554B2

公开(公告)日：2019-06-18

申请号：US15790732

申请日：2017-10-23

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Dongliang Dun ,  Zhiqiang Xia ,  Jine Liu ,  Feng Qin

IPC: G06F3/045 ,  G06F3/041 ,  G02F1/1333 ,  G02F1/1343

Abstract: An array substrate, a manufacturing method, a touch display panel, a touch display apparatus are provided. The manufacturing method includes: forming a gate on a substrate; forming a first insulating layer covering the gate; forming an active layer and a sensing resistor; forming a first electrode layer covering the sensing resistor; forming a source and a drain; etching the first doped layer at a part being not overlapped with the source and the drain, reserving the first electrode layer to cover the sensing resistor; forming a second insulating layer covering the source and the drain; etching the second insulating layer at a part being overlapped with the sensing resistor to expose the first electrode layer; forming a second electrode layer, and etching the first/second electrode layer at a part where the first/second electrode layer is overlapped with the sensing resistor to expose the sensing resistor.

公开(公告)号：US20180046300A1

公开(公告)日：2018-02-15

申请号：US15790732

申请日：2017-10-23

Applicant: Shanghai AVIC OPTO Electronics Co., Ltd.

Inventor： Dongliang DUN ,  Zhiqiang Xia ,  Jine Liu ,  Feng Qin

IPC: G06F3/041 ,  G02F1/1333 ,  G02F1/1343 ,  G06F3/045

CPC classification number: G06F3/0412 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/1343 ,  G06F3/0414 ,  G06F3/045 ,  G06F2203/04103 ,  G06F2203/04105

Abstract: An array substrate, a manufacturing method, a touch display panel, a touch display apparatus are provided. The manufacturing method includes: forming a gate on a substrate; forming a first insulating layer covering the gate; forming an active layer and a sensing resistor; forming a first electrode layer covering the sensing resistor; forming a source and a drain; etching the first doped layer at a part being not overlapped with the source and the drain, reserving the first electrode layer to cover the sensing resistor; forming a second insulating layer covering the source and the drain; etching the second insulating layer at a part being overlapped with the sensing resistor to expose the first electrode layer; forming a second electrode layer, and etching the first/second electrode layer at a part where the first/second electrode layer is overlapped with the sensing resistor to expose the sensing resistor.