公开(公告)号：US20070007244A1

公开(公告)日：2007-01-11

申请号：US11160671

申请日：2005-07-05

申请人： Habib Hichri ,  Kaushik Kumar ,  Helen Maynard

发明人： Habib Hichri ,  Kaushik Kumar ,  Helen Maynard

IPC分类号： G01L21/30 ,  H01L21/306 ,  C23F1/00 ,  B44C1/22

CPC分类号： G01M3/226 ,  H01J37/32623 ,  H01J37/32935 ,  H01L21/67069

摘要： A system and method for detecting a loss of plasma confinement. The system includes a plasma chamber that includes a plasma space and a non-plasma space. A plasma apparatus generates a plasma within the plasma space. The non-plasma space surrounds the plasma space and is separated from the plasma space by a confinement barrier that is adapted to confine the plasma in the plasma space during performance of an operational process by the plasma on a substrate disposed within the plasma space. Plasma detectors distributed on bounding surfaces of the non-plasma space are adapted to detect plasma that has escaped from the plasma space during performance of the operational process. The operational process is performed while the plasma detectors are monitoring the non-plasma space for a presence of the escaped plasma in the non-plasma space. If the monitoring has detected the escaped plasma, then the operational process is aborted.

摘要翻译： 一种用于检测血浆约束损失的系统和方法。 该系统包括等离子体室，其包括等离子体空间和非等离子体空间。 等离子体装置在等离子体空间内产生等离子体。 非等离子体空间围绕等离子体空间，并且通过限制屏障与等离子体空间分离，该限制屏障适于在等离子体在等离子体空间内的衬底上的等离子体执行操作过程期间将等离子体限制在等离子体空间中。 分布在非等离子体空间的边界表面上的等离子体检测器适于检测在执行操作过程期间已经从等离子体空间逸出的等离子体。 在等离子体检测器正在监测非等离子体空间以在非等离子体空间中存在逸出的等离子体的同时执行操作过程。 如果监测检测到逃逸的等离子体，则操作过程中止。

公开(公告)号：US07888252B2

公开(公告)日：2011-02-15

申请号：US12372174

申请日：2009-02-17

申请人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

发明人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76829

摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

摘要翻译： 一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充 具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。 填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开 在门区域上至少有一个块。 在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。

公开(公告)号：US20080099923A1

公开(公告)日：2008-05-01

申请号：US11968929

申请日：2008-01-03

申请人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

发明人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

IPC分类号： H01L23/48

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔线路电平低k电介质层，其上具有金属线导体，其具有底部和侧壁; 在第一多孔线路低k电介质上的抛光停止层; 第二薄的无孔通孔级低k电介质层，用于涂覆和平坦化线和通孔侧壁; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。

公开(公告)号：US20100210098A1

公开(公告)日：2010-08-19

申请号：US12372174

申请日：2009-02-17

申请人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

发明人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

IPC分类号： H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76829

摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

摘要翻译： 一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充 具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。 填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开 在门区域上至少有一个块。 在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。

公开(公告)号：US20080042174A1

公开(公告)日：2008-02-21

申请号：US11923075

申请日：2007-10-24

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

公开(公告)号：US20060124993A1

公开(公告)日：2006-06-15

申请号：US10905041

申请日：2004-12-13

申请人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

IPC分类号： H01L29/76

CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

摘要： A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.

摘要翻译： 一种新颖的晶体管结构及其制造方法。 晶体管结构包括（a）衬底和（b）衬底上的半导体区域，栅极介电区域和栅极区域，其中栅极电介质区域夹在半导体区域和栅极区域之间，其中半导体区域 通过所述栅极电介质区域与所述栅极区域电绝缘，其中所述半导体区域包括沟道区域和第一和第二源极/漏极区域，其中所述沟道区域夹在所述第一和第二源极/漏极区域之间，其中所述第一和/ 第二源极/漏极区域与栅极区域对准，其中沟道区域和栅极电介质区域（i）共享基本上垂直于衬底顶表面的界面，以及（ii）不共享任何界面表面 其基本上平行于衬底的顶表面。

公开(公告)号：US20060118961A1

公开(公告)日：2006-06-08

申请号：US11341338

申请日：2006-01-26

申请人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

发明人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

IPC分类号： H01L23/48

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.