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公开(公告)号：US20230135509A1
公开(公告)日：2023-05-04
申请号：US17581611
申请日：2022-01-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
Inventor： Yen-Chun Huang , Shu Ling Liao , Fang-Yi Liao , Yu-Chang Lin
IPC: H01L21/8234 , H01L27/088 , H01L21/3115
Abstract: A semiconductor device and a method of forming the same are provided. A device includes a substrate, a first isolation structure over the substrate, a first fin and a second fin over the substrate and extending through the first isolation structure, and a hybrid fin extending into the first isolation structure and interposed between the first fin and the second fin. A top surface of the first fin and a top surface of the second fin are above a top surface of the first isolation structure. A top surface of the hybrid fin is above the top surface of the first isolation structure. The hybrid fin includes an upper region, and a lower region under the upper region. The lower region includes a seam. A topmost portion of the seam is below the top surface of the first fin and the top surface of the second fin.
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公开(公告)号：US11640986B2
公开(公告)日：2023-05-02
申请号：US17363645
申请日：2021-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chang Lin , Tien-Shun Chang , Szu-Ying Chen , Chun-Feng Nieh , Sen-Hong Syue , Huicheng Chang
IPC: H01L29/76 , H01L29/66 , H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/265 , H01L21/324
Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.
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公开(公告)号：US11574907B2
公开(公告)日：2023-02-07
申请号：US17170601
申请日：2021-02-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yu-Chang Lin , Chun-Feng Nieh , Huicheng Chang , Hou-Yu Chen , Yong-Yan Lu
IPC: H01L27/092 , H01L29/78 , H01L29/66 , H01L27/12 , H01L29/49 , H01L29/165 , H01L21/265 , H01L21/8234 , H01L21/8238 , H01L21/02 , H01L21/84
Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
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公开(公告)号：US20220367686A1
公开(公告)日：2022-11-17
申请号：US17529394
申请日：2021-11-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chang Lin , Liang-Yin Chen , Chun-Feng Nieh , Huicheng Chang , Yee-Chia Yeo
IPC: H01L29/66 , H01L21/8234 , H01L21/324 , H01L29/78 , H01L29/08
Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.
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公开(公告)号：US20220319930A1
公开(公告)日：2022-10-06
申请号：US17824610
申请日：2022-05-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chang Lin , Chun-Feng Nieh , Huicheng Chang , Yee-Chia Yeo
IPC: H01L21/8234 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78
Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.
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公开(公告)号：US11348835B2
公开(公告)日：2022-05-31
申请号：US17119102
申请日：2020-12-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chang Lin , Chun-Feng Nieh , Huicheng Chang , Yee-Chia Yeo
IPC: H01L21/8234 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78
Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.
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公开(公告)号：US20210328044A1
公开(公告)日：2021-10-21
申请号：US17363645
申请日：2021-06-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chang Lin , Tien-Shun Chang , Szu-Ying Chen , Chun-Feng Nieh , Sen-Hong Syue , Huicheng Chang
IPC: H01L29/66 , H01L27/092 , H01L29/78 , H01L21/8238 , H01L21/265 , H01L21/324
Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.
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公开(公告)号：US10763363B2
公开(公告)日：2020-09-01
申请号：US15949273
申请日：2018-04-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jyun-Hao Lin , Chun-Feng Nieh , Huicheng Chang , Yu-Chang Lin
IPC: H01L29/78 , H01L29/10 , H01L29/66 , H01L29/08 , H01L29/167 , H01L29/36 , H01L21/265 , H01L29/165 , H01L27/092 , H01L21/8238 , H01L21/02 , H01L27/11 , H01L21/306
Abstract: An embodiment is a method of manufacturing a semiconductor device. The method includes forming a fin on a substrate. A gate structure is formed over the fin. A recess is formed in the fin proximate the gate structure. A gradient doped region is formed in the fin with a p-type dopant. The gradient doped region extends from a bottom surface of the recess to a vertical depth below the recess in the fin. A source/drain region is formed in the recess and on the gradient doped regions.
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公开(公告)号：US10056383B2
公开(公告)日：2018-08-21
申请号：US15446295
申请日：2017-03-01
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yu-Chang Lin , Chun-Feng Nieh , Huicheng Chang , Hou-Yu Chen , Yong-Yan Lu
IPC: H01L29/78 , H01L27/092 , H01L29/66 , H01L27/12 , H01L21/8238 , H01L21/265 , H01L21/8234 , H01L21/02 , H01L29/49 , H01L21/20 , H01L21/336 , H01L29/165
CPC classification number: H01L27/0924 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/26593 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L27/1211 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/66803 , H01L29/6681 , H01L29/7842 , H01L29/7846 , H01L29/7848 , H01L29/785 , H01L29/7851 , H01L29/7855
Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
