公开(公告)号：US4720830A

公开(公告)日：1988-01-19

申请号：US803351

申请日：1985-12-02

申请人： Sunil P. Joshi ,  Venkatraman Iyer

发明人： Sunil P. Joshi ,  Venkatraman Iyer

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  G06F11/12

CPC分类号： H03M13/091

摘要： There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a group clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant group of the checksum register. A group wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the groups of CRC data can be shifted into position through the array one group per each cycle of the group clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several different architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be peformed on all groups of a message while excluding some selected number of bits in the first group is also disclosed.

摘要翻译： 这里公开了CRC计算电路，其可以计算每组每个时钟周期的8位原始输入数据的CRC校验位。 计算装置使用8行移位链接，每行的输入耦合到前一行的数据输出。 每个移动链路将其输入位移位到最高有效位的一位位置，并且所选择的移位链路在它们的输入位和输入异或门的输出之间执行异或运算，其异或运算的一个输入位与 最重要的一组校验和寄存器中的位。 组宽输出总线用于通过在输出周期期间禁用移位链路阵列来访问来自校验和寄存器的最终校验位，以便每组每组CRC循环中的CRC数据组可以移位到阵列中 时钟。 提供用于将所有逻辑1强制到第一行移位链路的数据输入的预设逻辑，使得可以在CRC计算的第一个时钟周期期间预设该机器。 公开了几种不同的体系结构，用于允许单独计算头部分组上的CRC比特和数据分组，其中数据分组上的CRC比特可以仅针对数据计算，或者数据加上头部的头部和CRC比特。 还公开了允许CRC计算在消息的所有组上被排除的逻辑，同时排除第一组中的某些选定位数。