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    Bitstream processing using coalesced buffers and delayed matching and enhanced memory writes
    33.
    发明授权
    Bitstream processing using coalesced buffers and delayed matching and enhanced memory writes 有权
    使用合并缓冲区和延迟匹配和增强存储器写入的位流处理

    公开(公告)号：US09203887B2

    公开(公告)日：2015-12-01

    申请号：US13994129

    申请日：2011-12-23

    申请人： Vinodh Gopal ,  Jim D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Deniz Karakoyunlu ,  Erdinc Ozturk ,  Martin Dixon ,  Kahraman Akdemir

    发明人： Vinodh Gopal ,  Jim D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Deniz Karakoyunlu ,  Erdinc Ozturk ,  Martin Dixon ,  Kahraman Akdemir

    IPC分类号： H04L29/06 ,  H04W28/06 ,  H03M7/30

    CPC分类号： H04L65/607 ,  H03M7/30 ,  H03M7/3086 ,  H04L65/608 ,  H04L69/04 ,  H04L69/22 ,  H04W28/06

    摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.

    摘要翻译： 用于处理比特流和字节流的方法和装置。 根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。 使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。 对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。 如果这样做，令牌的len值通过使用合并缓冲区来添加。 在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。 还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器） 检测位累加器是满或接近满的操作。

    Instructions processors, methods, and systems to process BLAKE secure hashing algorithm
    34.
    发明授权
    Instructions processors, methods, and systems to process BLAKE secure hashing algorithm 有权
    指令处理器，方法和系统来处理BLAKE安全散列算法

    公开(公告)号：US09100184B2

    公开(公告)日：2015-08-04

    申请号：US13976741

    申请日：2011-12-22

    申请人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

    发明人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

    IPC分类号： H04L29/00 ,  H04L9/28 ,  H04L9/06 ,  G06F21/72

    CPC分类号： H04L9/28 ,  G06F9/30007 ,  G06F9/30036 ,  G06F21/72 ,  H04L9/0643 ,  H04L2209/122

    摘要： A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function.

    摘要翻译： 一种方面的方法包括：接收指示具有至少一组四个状态矩阵数据元素的第一源的指令，其表示对密码散列算法的G函数的四个输入的完整集合。 该算法使用十六个数据元素状态矩阵，并在列和对角线之间更新数据元素。 该指令还指示具有表示消息和常数数据的数据元素的第二源。 响应该指令，结果存储在指令指示的目的地中。 结果包括更新的状态矩阵数据元素，包括至少一组四个更新的状态矩阵数据元素。 四个更新的状态矩阵数据元素中的每一个表示已由G功能更新的第一源的四个状态矩阵数据元素中的相应一个。

    BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES
    36.
    发明申请
    BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES 有权
    使用加密缓存和延迟匹配和增强存储器写入的BITSTREAM处理

    公开(公告)号：US20140156790A1

    公开(公告)日：2014-06-05

    申请号：US13994129

    申请日：2011-12-23

    申请人： Vinodh Gopal ,  Jim D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghail ,  Deniz Karakoyunlu ,  Erdinc Ozturk ,  Martin Dixon ,  Kahraman Akdemir

    发明人： Vinodh Gopal ,  Jim D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghail ,  Deniz Karakoyunlu ,  Erdinc Ozturk ,  Martin Dixon ,  Kahraman Akdemir

    IPC分类号： H04L29/06

    CPC分类号： H04L65/607 ,  H03M7/30 ,  H03M7/3086 ,  H04L65/608 ,  H04L69/04 ,  H04L69/22 ,  H04W28/06

    摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.

    摘要翻译： 用于处理比特流和字节流的方法和装置。 根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。 使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。 对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。 如果这样做，令牌的len值通过使用合并缓冲区来添加。 在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。 还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器） 检测位累加器是满或接近满的操作。

    METHOD AND APPARATUS TO PROCESS 4-OPERAND SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION
    37.
    发明申请
    METHOD AND APPARATUS TO PROCESS 4-OPERAND SIMD INTEGER MULTIPLY-ACCUMULATE INSTRUCTION 有权
    过程4操作的方法和装置SIMD INTEGER MULTIPLY-ACCUMULATE指令

    公开(公告)号：US20140082328A1

    公开(公告)日：2014-03-20

    申请号：US13617021

    申请日：2012-09-14

    申请人： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford ,  Gilbert M. Wolrich

    发明人： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford ,  Gilbert M. Wolrich

    IPC分类号： G06F9/302 ,  G06F9/30

    CPC分类号： G06F9/3001 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/3887

    摘要： According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.

    摘要翻译： 根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。 第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。 所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到 基于第四操作数的累计值。

    Storage Accelerator
    39.
    发明申请
    Storage Accelerator 有权
    存储加速器

    公开(公告)号：US20080162806A1

    公开(公告)日：2008-07-03

    申请号：US11617966

    申请日：2006-12-29

    申请人： Vinodh Gopal ,  Yogesh Bansal ,  Gilbert M. Wolrich ,  Wajdi Feghali ,  Kirk Yap

    发明人： Vinodh Gopal ,  Yogesh Bansal ,  Gilbert M. Wolrich ,  Wajdi Feghali ,  Kirk Yap

    IPC分类号： G06F12/06

    CPC分类号： G06F11/1076 ,  G06F2211/1057

    摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

    摘要翻译： 本公开提供了一种用于生成RAID综合征的方法。 在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。 该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。 该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。 该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。