公开(公告)号：US07692968B2

公开(公告)日：2010-04-06

申请号：US11782149

申请日：2007-07-24

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/26

摘要： An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.

摘要翻译： 提供了一种非易失性存储器的操作方法。 操作方法是对所选择的基于氮化物的存储单元执行读取操作，将第一正电压施加到与所选存储单元的一侧相邻的字线，并且将第二正电压施加到相邻的另一个字线 到所选存储单元的另一侧。 本发明的操作方法不仅可以减少耦合干扰问题，而且可以获得更宽的操作窗口。

公开(公告)号：US06683352B2

公开(公告)日：2004-01-27

申请号：US10078314

申请日：2002-02-15

申请人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L2976

CPC分类号： H01L21/823425 ,  H01L21/823443 ,  H01L29/4238 ,  H01L29/665

摘要： A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.

摘要翻译： 公开了一种金属氧化物半导体场效应晶体管结构。 p型栅极，设置在半导体衬底上。 栅极电介质层设置在p型栅极和半导体衬底之间。 漏极区域设置在半导体衬底内，其中漏极区域被p型栅极包围。 源极区域设置在半导体衬底内，其中源极区域围绕p形栅极。 在源极/漏极区域和p形栅极上设置硅化物结构。

公开(公告)号：US06549029B1

公开(公告)日：2003-04-15

申请号：US09990261

申请日：2001-11-20

申请人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Tsung-Hsuan Hsieh ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G01R3126

CPC分类号： G01R27/2605

摘要： A circuit structure for measuring a capacitive load. The capacitive load is coupled between a first and a second nodes, and drains of a first PMOS and a first NMOS transistors are coupled to the first node, and drains of a second PMOS and a second NMOS transistors are coupled to the second node, and a pad is coupled to the second node. First, sources of the first and the second PMOS transistors and sources of the first and the second NMOS transistors are biased at a power source and a ground respectively. A non-synchronized voltage is applied to gates of the first and the second PMOS transistors and to gates of the first and the second NMOS transistors simultaneously. By grounding and floating the pad, a current flowing through the capacitive load is obtained to calculate the capacitance.

摘要翻译： 用于测量电容性负载的电路结构。 电容性负载耦合在第一和第二节点之间，并且第一PMOS和第一NMOS晶体管的漏极耦合到第一节点，并且第二PMOS和第二NMOS晶体管的漏极耦合到第二节点，并且 垫连接到第二节点。 首先，第一和第二PMOS晶体管的源极和第一和第二NMOS晶体管的源极分别偏置在电源和地。 非同步电压同时施加到第一和第二PMOS晶体管的栅极和第一和第二NMOS晶体管的栅极。 通过接地和浮动焊盘，获得流过电容性负载的电流来计算电容。

公开(公告)号：US20110038208A1

公开(公告)日：2011-02-17

申请号：US12914020

申请日：2010-10-28

申请人： Yao-Wen CHANG ,  Tao-Cheng Lu

发明人： Yao-Wen CHANG ,  Tao-Cheng Lu

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/0475 ,  G11C16/28

摘要： A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.

摘要翻译： 读取双位存储单元的方法包括控制终端，第一终端和第二终端。 双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。 首先，分别对控制端子和第一端子施加控制电压和读取电压。 第二端子接地以测量第一端子的第一输出电流值。 然后，控制电压和读取电压分别施加到控制端子和第二端子。 第一端子接地以测量第二端子的第二输出电流值。 之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。

公开(公告)号：US20080266966A1

公开(公告)日：2008-10-30

申请号：US11782149

申请日：2007-07-24

申请人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/26

摘要： An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.

摘要翻译： 提供了一种非易失性存储器的操作方法。 操作方法是对所选择的基于氮化物的存储单元执行读取操作，将第一正电压施加到与所选存储单元的一侧相邻的字线，并且将第二正电压施加到相邻的另一个字线 到所选存储单元的另一侧。 本发明的操作方法不仅可以减少耦合干扰问题，而且可以获得更宽的操作窗口。

公开(公告)号：US06465849B1

公开(公告)日：2002-10-15

申请号：US10072318

申请日：2002-02-07

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H01L2976

CPC分类号： H01L27/0629

摘要： A CMOS structure having a dynamic threshold voltage comprising of a MOS transistor, a first diode and a second diode. A first terminal of the first diode is coupled to the gate terminal of the MOS transistor and a second terminal of the first diode is coupled to the substrate of the MOS transistor. The first terminal of the second diode is coupled to a bulk voltage terminal and a second terminal of the second diode is coupled to the substrate of the MOS transistor.

摘要翻译： 具有包括MOS晶体管，第一二极管和第二二极管的动态阈值电压的CMOS结构。 第一二极管的第一端子耦合到MOS晶体管的栅极端子，并且第一二极管的第二端子耦合到MOS晶体管的衬底。 第二二极管的第一端子耦合到体电压端子，第二二极管的第二端子连接到MOS晶体管的衬底。

公开(公告)号：US08675322B2

公开(公告)日：2014-03-18

申请号：US13105270

申请日：2011-05-11

申请人： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Shih-Yu Wang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection device electronically connected to a pad is provided. The ESD protection device includes K PNP transistors and a protection circuit, wherein K is a positive integer. An emitter of the 1st PNP transistor is electronically connected to the pad, a base of the ith PNP transistor is electronically connected to an emitter of the (i+1)th PNP transistor, and collectors of the K PNP transistors are electronically connected to a ground, wherein i is an integer and 1≦i≦(K−1). The protection circuit is electronically connected between a base of the Kth PNP transistor and the ground and provides a discharge path. An electrostatic signal from the pad is conducted to the ground through the discharge path and the K PNP transistors.

摘要翻译： 提供电连接到垫的静电放电（ESD）保护装置。 ESD保护器件包括K PNP晶体管和保护电路，其中K是正整数。 第一PNP晶体管的发射极电连接到焊盘，第i PNP晶体管的基极电连接到第（i + 1）PNP晶体管的发射极，并且K PNP晶体管的集电极电连接到 地面，其中i是整数和1 @ i @（K-1）。 保护电路电连接在第K PNP晶体管的基极与地之间并提供放电路径。 来自焊盘的静电信号通过放电路径和K PNP晶体管传导到地面。

公开(公告)号：US08259492B2

公开(公告)日：2012-09-04

申请号：US12914020

申请日：2010-10-28

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/28

摘要： A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.

摘要翻译： 读取双位存储单元的方法包括控制终端，第一终端和第二终端。 双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。 首先，分别对控制端子和第一端子施加控制电压和读取电压。 第二端子接地以测量第一端子的第一输出电流值。 然后，控制电压和读取电压分别施加到控制端子和第二端子。 第一端子接地以测量第二端子的第二输出电流值。 之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。

公开(公告)号：US06829174B2

公开(公告)日：2004-12-07

申请号：US10248572

申请日：2003-01-30

申请人： Yao-Wen Chang ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Tao-Cheng Lu

IPC分类号： G11C700

CPC分类号： G11C16/16 ,  G11C16/10

摘要： A method of narrowing the threshold voltage distribution in a memory. The method includes separating the erase and erase identification of odd memory cells from the erase and erase identification of even memory cells in an advanced non-volatile memory so that the distribution of the threshold voltage is narrowed.

摘要翻译： 缩小存储器中的阈值电压分布的方法。 该方法包括将奇数存储器单元的擦除和擦除识别与高级非易失性存储器中的偶数存储器单元的擦除和擦除识别分离，使得阈值电压的分布变窄。

公开(公告)号：US06624737B2

公开(公告)日：2003-09-23

申请号：US10060376

申请日：2002-02-01

申请人： Yao-Wen Chang ,  Hui-Chih Lin ,  Tao-Cheng Lu

发明人： Yao-Wen Chang ,  Hui-Chih Lin ,  Tao-Cheng Lu

IPC分类号： H01C706

CPC分类号： H01L27/0802 ,  G05F1/46

摘要： This invention relates to a voltage regulated circuit, more particularly, to a voltage regulated circuit with a well resistor divider. The present invention applies two well resistors act as the voltage regulated circuit and uses the characteristic of the well resistor in the resistance value, which is increased following the voltage that is transmitted to the well resistor to make an output voltage become a stable value. When the input voltage is an instable and over-high value, the depletion region in the well resistor will extend to absorb the over-high voltage value and make the output voltage to become a stable voltage value.

摘要翻译： 本发明涉及一种电压调节电路，更具体地说，涉及一种具有阱电阻分压器的电压调节电路。 本发明使用两个阱电阻器作为电压调节电路，并且使用电阻值中的阱电阻器的特性，其随着传输到阱电阻器的电压而增加以使输出电压变为稳定值。 当输入电压为不稳定和过高值时，阱电阻器中的耗尽区域将延伸以吸收过高的电压值，并使输出电压变为稳定的电压值。