公开(公告)号：US11307502B2

公开(公告)日：2022-04-19

申请号：US16952245

申请日：2020-11-19

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Feng Bai ,  Wanjuan Zhang ,  Yibin Huang ,  Yao Xu ,  Fan Zhang

IPC分类号： H01L21/027 ,  G03F7/20

摘要： Embodiments and implementations of the present disclosure provide assistant pattern configuration methods, masks and forming methods thereof, and related devices. One form of a configuration method includes: providing a main pattern having an edge extending along a first direction, where a second direction is perpendicular to the first direction, the main pattern having a first optimal focal plane in the first direction and a second optimal focal plane in the second direction when exposed, and where there is an optimal focal plane offset between the first optimal focal plane and the second optimal focal plane; providing an initial assistant pattern around the main pattern; extracting a configuration parameter of the initial assistant pattern, the configuration parameter corresponding to the optimal focal plane offset; obtaining configuration information corresponding to a preset optimal focal plane offset based on an adjustment of the configuration parameter; and configuring an assistant pattern around the main pattern according to the configuration information. Embodiments and implementations of the present disclosure can improve lithographic quality.

公开(公告)号：US20220115264A1

公开(公告)日：2022-04-14

申请号：US17645888

申请日：2021-12-23

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Shengfen CHIU ,  Liang CHEN ,  Liang HAN

IPC分类号： H01L21/764 ,  H01L21/311 ,  H01L29/51 ,  H01L27/11521 ,  H01L29/49 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/06

摘要： A method for manufacturing a flash memory device is provided. The method includes: providing a substrate structure including a substrate, a plurality of active regions and a plurality of first isolation regions alternately arranged in a first direction and extending in a second direction different from the first direction, a plurality of gate structures on the substrate, the gate structures being spaced apart from each other and extending in the second direction, and a gap structure between the gate structures; forming an overhang surrounding an upper portion of the gate structures to form a gap structure between the gate structures; and forming a second isolation region filling an upper portion of the gap structures and leaving a first air gap between the gap structures.

公开(公告)号：US11303267B2

公开(公告)日：2022-04-12

申请号：US17017139

申请日：2020-09-10

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yan Fei Cai ,  Kai Hua Hou ,  Yuan Chai ,  Jian Chen ,  Jun Wang

IPC分类号： H03K3/037 ,  H03K3/012 ,  H03K3/3562

摘要： A flip-flop is provided. The flip-flop includes: a first inverter including an input terminal to receive data signal and an output terminal coupled to an input terminal of the master latch, a second inverter, a master latch including an output terminal coupled to an input terminal of a slave latch, and the slave latch including an output terminal coupled to an input terminal of the second inverter. An output terminal of the second inverter is configured as an output terminal of the flip-flop. A duration of the first clock signal inputted to the master latch is greater than a duration of the first clock signal inputted to the slave latch. A duration of the second clock signal inputted to the master latch is greater than a duration of the second clock signal inputted to the slave latch.

公开(公告)号：US11302803B2

公开(公告)日：2022-04-12

申请号：US17034335

申请日：2020-09-28

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Haiyang Zhang ,  Panpan Liu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/417

摘要： Semiconductor structure and fabrication method are provided. The method includes providing a substrate including a first region and a second region; forming a plurality of fins on the first region of the substrate; forming a first isolation structure on the first region and the second region of the substrate; forming a gate structure and a dummy gate structure each across fins and the first isolation structure at the first region; forming an epitaxial layer in each fin on two sides of the gate structure; forming a first opening by etching a portion of each of the first isolation structure and the substrate that are at the second region; filling the first opening with a conductive material layer; removing the dummy gate structure and a portion of the conductive material layer in the first opening to form a power rail; and forming a second isolation structure in a second opening.

公开(公告)号：US11295795B2

公开(公告)日：2022-04-05

申请号：US16864607

申请日：2020-05-01

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Tengye Wang ,  Jiaxu Peng ,  Tao Wang ,  Zijian Zhao

IPC分类号： G11C11/16

摘要： The present disclosure provides a data reading circuit and a storage unit. The data reading circuit includes a being read unit connected to a voltage stabilizing unit and configured to store data. The voltage stabilizing unit is configured to stabilize and output a current from the being read unit to a first amplifying unit. The first amplifying unit is configured to amplify and output the current from the being read unit to a comparing unit. A reference unit is connected to a second amplifying unit, to output a reference current to the second amplifying unit. The second amplifying unit is configured to amplify and output the reference current to the comparing unit. The comparing unit is configured to compare a comparing point voltage, that is based on the amplified current of the being read unit and the amplified reference current, with a reference voltage and to output comparison results.

公开(公告)号：US20220102205A1

公开(公告)日：2022-03-31

申请号：US17229255

申请日：2021-04-13

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： He ZUOPENG ,  Yang MING ,  Bei DUOHUI

IPC分类号： H01L21/768 ,  H01L21/033

摘要： A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base; forming a pattern memory layer on the base, where at least a first trench and a second trench are provided on the pattern memory layer, where an extending direction of the first trench is parallel to an extending direction of the second trench, and the first trench and the second trench are formed using different masks; and forming mandrel lines separated on the base at positions of the base that correspond to the first trench and the second trench. By using the method, a problem that a photoresist peels off during etching due to an elongated shape when separated mandrel lines are directly formed can be avoided. Further, a problem of a relatively high requirement on a filling material when the mandrel lines are formed directly by using a plurality of photolithography processes can be avoided, to lower the requirement on the filling material.

公开(公告)号：US11276608B2

公开(公告)日：2022-03-15

申请号：US16863343

申请日：2020-04-30

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Wang Wei ,  Su Bo ,  Hu You Cun

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/311

摘要： A semiconductor structure and a forming method thereof are provided. The forming method includes: providing a base, where a mask material layer is formed on the base, a plurality of first trenches disposed at intervals are formed in the mask material layer, an extension direction of the first trenches is a first direction, the plurality of first trenches are arranged in parallel along a second direction, and the second direction is perpendicular to the first direction; forming a first side wall covering layer and a barrier layer, where the first side wall covering layer is located on a side wall of the first trench, the barrier layer is located in at least one of the first trenches, the barrier layer divides the first trench in the first direction, and the first side wall covering layer exposes side walls of the barrier layer on two sides in the first direction; forming a second side wall covering layer on the side walls of the barrier layer exposed by the first side wall covering layer; and etching the mask material layer between the adjacent first trenches by using the first side wall covering layer, the second side wall covering layer and the barrier layer as a mask to form a second trench, where the second trench is isolated from the first trench by the first side wall covering layer. According to the present disclosure, the barrier layer is protected by the second side wall covering layer, thereby improving the accuracy of pattern transfer.

公开(公告)号：US11257863B2

公开(公告)日：2022-02-22

申请号：US15898189

申请日：2018-02-15

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION

发明人： Yibin Song ,  Zhuofan Chen

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic random access memory includes a memory cell including a first fixed layer, a second fixed layer, and one or more free layers disposed between the first fixed layer and the second fixed layer. The first and second fixed layers are continuous layers and commonly shared by a plurality of memory cells. The magnetic random access memory has a relatively simple structure that not only reduces magnetic interference between memory cells, but also simplifies the fabrication process and increases the integration level.

公开(公告)号：US11251089B2

公开(公告)日：2022-02-15

申请号：US16984604

申请日：2020-08-04

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei Zhou

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  C23F1/00

摘要： A semiconductor device is provided. The semiconductor device includes a base substrate, which include a first region having a first transistor and a second region having a second transistor, the first transistor having a working current smaller than the second transistor. The semiconductor device further includes a first gate electrode on the first region of the base substrate, a second gate electrode on the second region of the base substrate and having an undercut structure, a first source/drain doped region in the base substrate on both sides of the first gate electrode, and a second source/drain doped region in the base substrate on both sides of the second gate electrode.

公开(公告)号：US20220037338A1

公开(公告)日：2022-02-03

申请号：US17104179

申请日：2020-11-25

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Nan WANG

IPC分类号： H01L27/11 ,  H01L23/522 ,  H01L29/78

摘要： A semiconductor structure and a forming method thereof are provided. The method includes: providing a base having a gate structure, where there is a gate cap layer on the top of the gate structure, there is a source/drain doped region in the base on two sides of the gate structure, there is a bottom dielectric layer on the base, the base includes a shared contact region that is used for forming a shared contact plug, the source/drain doped region located in the shared contact region is used as a first source/drain doped region, and the remaining is used as a second source/drain doped region; forming, in a bottom dielectric layer, a first source-drain interconnection layer connected to the second source/drain doped region, and a source/drain cap layer located on the top of the first source-drain interconnection layer; forming, in the bottom dielectric layer, a second source-drain interconnection layer connected to the first source/drain doped region; forming a top dielectric layer covering the gate cap layer, the source/drain cap layer, the second source-drain interconnection layer, and the bottom dielectric layer; and forming, in the shared contact region, a shared contact plug running through the top dielectric layer and the gate cap layer. According to the present disclosure, difficulty in forming the shared contact plug is reduced, and the performance of the semiconductor structure is improved.