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356 条记录 (耗时 0.019 秒)

    Apparatus and method of authenticating Joint Test Action Group (JTAG)
    31.
    发明申请
    Apparatus and method of authenticating Joint Test Action Group (JTAG) 有权
    联合测试行动小组（JTAG）认证的设备和方法

    公开(公告)号：US20100153797A1

    公开(公告)日：2010-06-17

    申请号：US12653082

    申请日：2009-12-08

    申请人： Yun-ho Youm ,  Mi-jung Noh ,  Hong-mook Choi ,  Xingguang Feng

    发明人： Yun-ho Youm ,  Mi-jung Noh ,  Hong-mook Choi ,  Xingguang Feng

    IPC分类号： G01R31/3177 ,  G06F11/25

    CPC分类号： G01R31/31705 ,  G01R31/31719 ,  G01R31/318566 ,  G01R31/318588

    摘要： In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed.

    摘要翻译： 在包括联合测试动作组（JTAG）认证装置的装置和使用该装置的JTAG认证方法中，该装置包括联合测试动作组（JTAG）认证装置，该装置包括确定是否存取的JTAG接入电路 根据预定协议的JTAG兼容设备，其管理所述JTAG兼容设备和所述设备，其中所述JTAG接入电路至少一个使内部总线和内部单元中的至少一个失效，并激活所述内部 总线线路和内部单元，根据是否访问JTAG兼容设备。

    Methods, apparatuses, and products for a secure circuit
    34.
    发明申请
    Methods, apparatuses, and products for a secure circuit 失效
    用于安全电路的方法，设备和产品

    公开(公告)号：US20100045337A1

    公开(公告)日：2010-02-25

    申请号：US12583371

    申请日：2009-08-19

    申请人： Philip Sydney Langton

    发明人： Philip Sydney Langton

    IPC分类号： H03K19/00

    CPC分类号： G01R31/318519 ,  G01R31/31719 ,  G06F21/445 ,  G06F2221/2129

    摘要： Methods, systems, apparatuses and products are disclosed for providing security circuits. Exemplary embodiments including semiconductor chips on circuit boards are shown, together with application in a movie stick/movie player pair.Such systems provide for and improve on the means for clocked logic security support beyond what is available in current security products while being capable of embodiment in low cost technologies such as programmable gate arrays.

    摘要翻译： 公开了用于提供安全电路的方法，系统，装置和产品。 示出了包括电路板上的半导体芯片的示例性实施例以及电影棒/电影播放器​​对中的应用。 这样的系统提供并改进了时钟逻辑安全支持的手段，超越了当前安全产品中可用的，同时能够以诸如可编程门阵列的低成本技术实现。

    Testing circuit and testing method for semiconductor device and semiconductor chip
    35.
    发明授权
    Testing circuit and testing method for semiconductor device and semiconductor chip 有权
    半导体器件和半导体芯片的测试电路和测试方法

    公开(公告)号：US07603248B2

    公开(公告)日：2009-10-13

    申请号：US11474393

    申请日：2006-06-26

    申请人： Hidetoshi Sugiyama ,  Masao Nakajima ,  Haruyuki Mouri ,  Hideaki Suzuki

    发明人： Hidetoshi Sugiyama ,  Masao Nakajima ,  Haruyuki Mouri ,  Hideaki Suzuki

    IPC分类号： G06F19/00

    CPC分类号： G01R31/31719 ,  G01R31/31701 ,  G01R31/31721

    摘要： A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.

    摘要翻译： 一种半导体器件的测试电路，具有测试模式，其中在对半导体器件进行测试之后无法读取关于内置存储器的信息，并且切割形成在划线区域中的焊盘。 划片PAD和划线ROM形成在晶片的切割区域中。 在芯片a上电时，上电复位电路将复位信号发送到模式寄存器。 将初始电阻值设置为“00”后，从模式开关端子输入模式切换信号，激活划线ROM，并设置测试模式。 在这个过程中，曼彻斯特编码信号由划片PAD提供，由时钟分频电路提供的分频时钟解码，设置模式寄存器中的测试模式中的寄存器的值，并且断言外部复位 或否定。

    Device and method for testing integrated circuit dice in an integrated circuit module
    36.
    发明授权
    Device and method for testing integrated circuit dice in an integrated circuit module 失效
    在集成电路模块中测试集成电路芯片的装置和方法

    公开(公告)号：US07519881B2

    公开(公告)日：2009-04-14

    申请号：US11389874

    申请日：2006-03-27

    申请人： Warren M. Farnworth ,  James M. Wark ,  Eric S. Nelson ,  Kevin G. Duesman

    发明人： Warren M. Farnworth ,  James M. Wark ,  Eric S. Nelson ,  Kevin G. Duesman

    IPC分类号： G01R31/28

    CPC分类号： G11C29/785 ,  G01R31/2884 ,  G01R31/31701 ,  G01R31/31719 ,  G01R31/318513 ,  G11C29/1201 ,  G11C29/46 ,  G11C29/80 ,  G11C29/808 ,  H01L22/22 ,  H01L2224/48091 ,  H01L2224/48227 ,  H04J2203/0062 ,  H01L2924/00014

    摘要： An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.

    摘要翻译： 诸如多芯片模块（MCM）的IC模块包括多个IC芯片，每个具有测试模式使能焊盘，例如输出使能焊盘。 集成到MCM基板中的保险丝将每个管芯的测试模式使能接合焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的一个接地 针脚。 通过向测试模式施加电源电压，使焊盘通过N / C引脚，在骰子中启动测试模式。 一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的接地电压使得接合焊盘通过接地引脚，使得电阻器禁用骰子中的测试模式并启动操作模式。 因此，封装在IC模块中的裸片可以在封装后进行测试。

    Electronic circuit comprising a secret sub-module
    37.
    发明授权
    Electronic circuit comprising a secret sub-module 有权
    电子电路包括秘密子模块

    公开(公告)号：US07519496B2

    公开(公告)日：2009-04-14

    申请号：US10571834

    申请日：2004-09-10

    申请人： Jean-Marc Yannou ,  Hervé Fleury ,  Hervé Vincent

    发明人： Jean-Marc Yannou ,  Hervé Fleury ,  Hervé Vincent

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318536 ,  G01R31/31719 ,  G01R31/318541 ,  G01R31/318555

    摘要： The invention relates to an electronic circuit including a sub-module assembly (2) connected to the rest of the circuit, the sub-module assembly including a secret sub-module (4) for performing a function, scan chains; a built-in self test circuit including a pattern generator (5) to apply input signals to the scan chains, and a signature register (6) to check output signals from the scan chains. In order to keep the sub-module secret, the scan chains are not connected to the rest of the circuit.

    摘要翻译： 本发明涉及一种包括连接到电路的其余部分的子模块组件（2）的电子电路，子模块组件包括用于执行功能的秘密子模块（4），扫描链; 包括用于向扫描链施加输入信号的模式发生器（5）的内置自检电路和用于检查来自扫描链的输出信号的签名寄存器（6）。 为了保持子模块的秘密，扫描链不连接到电路的其余部分。

    DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS
    38.
    发明申请
    DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS 有权
    通过光学手段防止集成电路反向工程的设备

    公开(公告)号：US20080252331A1

    公开(公告)日：2008-10-16

    申请号：US12140714

    申请日：2008-06-17

    申请人： Jeffrey A. Kash ,  James C. Tsang ,  Daniel R. Knebel

    发明人： Jeffrey A. Kash ,  James C. Tsang ,  Daniel R. Knebel

    IPC分类号： H01L27/15

    CPC分类号： H01L23/576 ,  G01R31/311 ,  G01R31/31719 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0207 ,  H01L2924/0002 ,  Y10S257/922 ,  H01L2924/00

    摘要： A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.

    摘要翻译： 提供了一种电子设备的方法，用于通过监视从电子设备中的晶体管和这种电活动设备发射的光发射来防止逆向工程。 该方法发射出与晶体管非常接近的无关随机光发射，以隐藏从晶体管发射的光发射图案。 作为一个特征，该装置可以包括基本上靠近晶体管的随机发光源，以在由源发射的随机光发射中隐藏来自晶体管的发射光的图案。 作为第二特征，设备可以通过随机延迟电耦合到晶体管的电信号来发射随机发光，并且响应于随机延迟的电信号，晶体管随机地发射光发射，从而隐藏单独的光模式 从晶体管发射的发射。

    Device for defeating reverse engineering of integrated circuits by optical means
    39.
    发明授权
    Device for defeating reverse engineering of integrated circuits by optical means 有权
    用于通过光学方式消除集成电路逆向工程的装置

    公开(公告)号：US07399992B2

    公开(公告)日：2008-07-15

    申请号：US11541997

    申请日：2006-10-02

    申请人： Jeffrey A. Kash ,  James C. Tsang ,  Daniel R. Knebel

    发明人： Jeffrey A. Kash ,  James C. Tsang ,  Daniel R. Knebel

    IPC分类号： H01L27/15

    CPC分类号： H01L23/576 ,  G01R31/311 ,  G01R31/31719 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0207 ,  H01L2924/0002 ,  Y10S257/922 ,  H01L2924/00

    摘要： An integrated circuit chip (IC) is equipped with a device for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in a circuit located in the IC. The device emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.

    摘要翻译： 集成电路芯片（IC）配备有通过监视位于IC中的电路中的晶体管和这种电活动器件发射的发光来防止逆向工程的装置。 器件发射离子晶体管非常近的多余的随机光发射，以隐藏从晶体管发射的光发射模式。 作为一个特征，该装置可以包括基本上靠近晶体管的随机发光源，以在由源发射的随机光发射中隐藏来自晶体管的发射光的图案。 作为第二特征，设备可以通过随机延迟电耦合到晶体管的电信号来发射随机发光，并且响应于随机延迟的电信号，晶体管随机地发射光发射，从而隐藏单独的光模式 从晶体管发射的发射。