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    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME
    31.
    发明申请
    SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME 有权
    半导体器件和半导体系统，包括它们

    公开(公告)号：US20150085590A1

    公开(公告)日：2015-03-26

    申请号：US14176837

    申请日：2014-02-10

    Applicant: SK hynix Inc.

    Inventor： Min Su KIM

    IPC: G11C7/10 ,  G11C7/06

    CPC classification number: G11C7/06 ,  G11C7/1048 ,  G11C2207/005

    Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller is suitable for generating command signals and address signals. The semiconductor device is suitable for electrically disconnecting a first local line from a second local line in response to an input control signal enabled in a read mode. The read mode is set according to a logic combination of the command signals. Further, the semiconductor device is suitable for sensing and amplifying a data on the first local line or the second local line according to the address signals to output the amplified data through an input/output line.

    Abstract translation: 提供半导体系统。 半导体系统包括控制器和半导体器件。 控制器适用于产生指令信号和地址信号。 半导体器件适于响应于在读取模式下启用的输入控制信号，将第一本地线路与第二本地线路电断开。 读取模式根据命令信号的逻辑组合来设置。 此外，半导体器件适用于根据地址信号来感测和放大第一本地线路或第二本地线路上的数据，以通过输入/输出线路输出放大的数据。

    Memory device and method for sensing a content of a memory cell
    33.
    发明授权
    Memory device and method for sensing a content of a memory cell 有权
    用于感测存储器单元的内容的存储器件和方法

    公开(公告)号：US08934315B2

    公开(公告)日：2015-01-13

    申请号：US13502378

    申请日：2009-11-12

    Applicant: Ido Levy ,  Lior Aviv ,  Eyal Hartmann

    Inventor： Ido Levy ,  Lior Aviv ,  Eyal Hartmann

    IPC: G11C7/06 ,  G11C7/12

    CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C2207/002 ,  G11C2207/005

    Abstract: A memory device to sense a content of a memory cell includes: a pair of bit-lines; a memory cell coupled between the bit-lines; and a sensing circuit. The sensing circuit has at least two inputs for receiving respective currents from a current conveyor, and senses, when operating in a sensing mode, a difference between output currents. The difference between the output currents represents a content of the memory cell. The sensing circuit includes an output for outputting an output signal that represents the content of the memory cell. The current conveyor isolates the sensing circuit from the bit-lines, when the current conveyor is operated in an isolation mode, and has at least two outputs for providing, to the sensing circuit, output currents representing bit-lines currents; and equalizing the output currents before the current conveyor starts to operate in a current conveying mode.

    Abstract translation: 用于感测存储器单元的内容的存储器件包括：一对位线; 耦合在位线之间的存储单元; 和感测电路。 感测电路具有至少两个用于接收来自当前传送器的相应电流的输入，并且在感测模式下操作时感测输出电流之间的差异。 输出电流之间的差异代表存储单元的内容。 感测电路包括用于输出表示存储器单元的内容的输出信号的输出。 当前输送机以隔离模式操作时，当前输送机将感测电路与位线隔离，并且具有至少两个输出，用于向感测电路提供表示位线电流的输出电流; 并且在当前输送机开始在当前输送模式下操作之前均衡输出电流。

    Semiconductor device
    34.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08929129B2

    公开(公告)日：2015-01-06

    申请号：US13946458

    申请日：2013-07-19

    Applicant: PS4 Luxco S.a.r.l.

    Inventor： Yumiko Yamamoto

    IPC: G11C11/00 ,  G05F3/02 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096

    CPC classification number: G05F3/02 ,  G11C7/1048 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/005

    Abstract: A device, comprising: first and second signal lines; first and second transistors of first conductivity type coupled in series between first and second signal lines and coupled to each other at first node; third and fourth transistors of second conductivity type coupled in series between first and second lines and coupled to each other at second node; power supply node coupled in common to first and second nodes; fifth transistor of first conductivity type coupled between first and second signal lines; and sixth transistor of second conductivity type coupled between first and second signal lines, wherein each of first, second and fifth transistors is configured to receive first control signal at gate electrode thereof, each of the third and fourth transistors is configured to receive second control signal at gate electrode thereof, and sixth transistor is configured to receive third control signal at gate electrode thereof.

    Abstract translation: 一种装置，包括：第一和第二信号线; 第一和第二导体类型的第一和第二晶体管串联耦合在第一和第二信号线之间并且在第一节点处彼此耦合; 第二导电类型的第三和第四晶体管串联耦合在第一和第二线之间并且在第二节点处彼此耦合; 电源节点共同耦合到第一和第二节点; 耦合在第一和第二信号线之间的第一导电类型的第五晶体管; 以及耦合在第一和第二信号线之间的第二导电类型的第六晶体管，其中第一，第二和第五晶体管中的每一个被配置为在其栅电极处接收第一控制信号，第三和第四晶体管中的每一个被配置为接收第二控制信号 在其栅电极处，并且第六晶体管被配置为在其栅电极处接收第三控制信号。

    Semiconductor Memory Device
    35.
    发明申请
    Semiconductor Memory Device 有权
    半导体存储器件

    公开(公告)号：US20150003178A1

    公开(公告)日：2015-01-01

    申请号：US14487379

    申请日：2014-09-16

    Applicant: PS4 Luxco S.a.r.l.

    Inventor： Keisuke Nomoto ,  Yuji Nakaoka

    IPC: G11C5/14 ,  G11C7/12

    CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4097 ,  G11C16/30 ,  G11C2207/005 ,  G11C2207/2227

    Abstract: A semiconductor device comprises a first pair of signal lines and a first control circuit. The first control circuit precharges each of the first pair of signal lines to a first voltage in response to a precharge signal, and changes the voltage level of each of the first pair of signal lines to a second voltage different from the first voltage when a deep power down signal is input.

    Abstract translation: 半导体器件包括第一对信号线和第一控制电路。 第一控制电路响应于预充电信号将第一对信号线中的每一个预充电到第一电压，并且当深度为第一对信号线时，将第一对信号线中的每一个的电压电平改变为与第一电压不同的第二电压 掉电信号被输入。

    Semiconductor device for supplying and measuring electric current through a pad
    37.
    发明授权
    Semiconductor device for supplying and measuring electric current through a pad 有权
    用于通过焊盘供应和测量电流的半导体器件

    公开(公告)号：US08854907B2

    公开(公告)日：2014-10-07

    申请号：US13590648

    申请日：2012-08-21

    Applicant: Sang Kug Lym ,  Dong Keun Kim

    Inventor： Sang Kug Lym ,  Dong Keun Kim

    IPC: G11C7/00

    CPC classification number: G11C13/0004 ,  G11C13/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2207/005

    Abstract: The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device capable of supplying and measuring an electric current through a pad. The semiconductor device includes a memory cell, a data pad configured to receive data to be programmed into the memory cell or a write current to be supplied to the memory cell from an external device, and output data read out from the memory cell or a cell current flowing from the memory cell to the external device, and a path switching unit configured to set up a path so that the memory cell and the data pad are directly coupled when a test operation is performed.

    Abstract translation: 半导体器件技术领域本发明涉及一种半导体器件，更具体地，涉及能够提供和测量通过焊盘的电流的半导体存储器件。 半导体器件包括存储单元，被配置为从外部设备接收要被编程到存储器单元中的数据或要从存储器单元提供给写入电流的数据焊盘，以及从存储单元或单元读出的数据 从存储单元流向外部设备的电流，以及路径切换单元，被配置为建立路径，使得当执行测试操作时，存储单元和数据区块直接耦合。

    Semiconductor memory device
    38.
    再颁专利
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：USRE45036E1

    公开(公告)日：2014-07-22

    申请号：US13779097

    申请日：2013-02-27

    Applicant: Conversant IP N.B. 868 Inc.

    Inventor： Hee-Bok Kang ,  Jin-Hong Ahn

    IPC: G11C7/00

    CPC classification number: G11C7/12 ,  G11C11/4094 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2227

    Abstract: A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar; a first second-type well including a first sense amplifying MOS transistor having a first-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar.

    Abstract translation: 半导体存储器件包括：第一第一型阱，其包括用于存储数据以将数据施加到第一位线和第一位线条之一的第一单元阵列;以及第一预充电MOS晶体管，其具有第二类型沟道 用于均衡第一位线和第一位线条的电压电平; 包括具有用于感测和放大第一位线和第一位线条之间的信号差的第一类型沟道的第一感测放大MOS晶体管和第一连接MOS晶体管的第一第二类型阱; 以及包括具有用于感测和放大第一位线和第一位线条之间的信号差的第二类型通道的第二读出放大MOS晶体管的第二第一型阱。

    NONVOLATILE MEMORY AND METHOD WITH IMPROVED I/O INTERFACE
    39.
    发明申请
    NONVOLATILE MEMORY AND METHOD WITH IMPROVED I/O INTERFACE 有权
    非易失性存储器和具有改进的I / O接口的方法

    公开(公告)号：US20140185374A1

    公开(公告)日：2014-07-03

    申请号：US13801142

    申请日：2013-03-13

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Venkatesh Prasad Ramachandra

    IPC: G11C16/06

    CPC classification number: G11C16/06 ,  G11C7/227 ,  G11C8/10 ,  G11C2207/005

    Abstract: Each I/O channel between a controller and one or more memory dice of a memory device has a driver on one end and a receiver at the other end. The receiver is optionally terminated with a pseudo open-drain (“POD”) termination instead of the conventional center-tapped (“CTT”) termination to save energy. During a read operation, data is driven from the memory die to a POD terminated receiver circuit in the controller. With POD termination, the degradation in performance due to the more non-linear driver in the memory die, fabricated for example in the NAND technology processing, is alleviated by an adaptive reference voltage level adjustment in the receiver circuit of the controller. Optionally, the receiver circuit of a memory die is also provided with an adaptive reference level adjustment.

    Abstract translation: 控制器与存储器件的一个或多个存储器管芯之间的每个I / O通道在一端具有驱动器，另一端具有接收器。 接收器可选择以假开放漏极（“POD”）端接而不是传统的中心抽头（“CTT”）终端来终止以节省能量。 在读取操作期间，数据从存储器管芯驱动到控制器中的POD端接的接收器电路。 通过POD终止，由于例如在NAND技术处理中制造的存储器管芯中的非线性驱动器的性能下降，通过控制器的接收器电路中的自适应参考电压电平调节来减轻。 可选地，存储管芯的接收器电路还具有自适应参考电平调整。

    NONVOLATILE SEMICONDUCTOR MEMORY
    40.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY 有权
    非易失性半导体存储器

    公开(公告)号：US20140173182A1

    公开(公告)日：2014-06-19

    申请号：US13831520

    申请日：2013-03-14

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Hiromitsu KOMAI

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0646 ,  G06F13/38 ,  G11C7/1048 ,  G11C16/00 ,  G11C16/24 ,  G11C2207/005 ,  G11C2207/2245

    Abstract: According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area.

    Abstract translation: 根据一个实施例，存储器包括暂时存储对阵列的读/写操作的数据的临时存储区域。 临时存储区域包括连接在第一数据总线和第二数据总线之间的钳位FET，连接在第一数据总线与第一电位之间的第一预充电FET，连接在第二数据总线与第一电位之间的第二预充电FET， 连接到第一数据总线的第一存储区域和连接到第二数据总线的第二存储区域。 控制电路被配置为当数据从第二存储区域传送到第一数据总线时被预充电到第一电位并且第二数据总线被预充电到低于第一电位的第二电位的预充电状态 第一个存储区域。

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