公开(公告)号：US20110253997A1

公开(公告)日：2011-10-20

申请号：US13087363

申请日：2011-04-14

Applicant: Sang Hee Park ,  Chi Sun Hwang ,  Chun Won Byun ,  Elvira M.C. Fortunato ,  Rodrigo F.P. Martins ,  Ana R.X. Barros ,  Nuno F.O. Correia ,  Pedro M.C. Barquinha ,  Vitor M.L. Figueiredo

Inventor： Sang Hee Park ,  Chi Sun Hwang ,  Chun Won Byun ,  Elvira M.C. Fortunato ,  Rodrigo F.P. Martins ,  Ana R.X. Barros ,  Nuno F.O. Correia ,  Pedro M.C. Barquinha ,  Vitor M.L. Figueiredo

IPC: H01L29/22 ,  H01L21/36

CPC classification number: H01L21/02565 ,  C23C14/08 ,  C23C14/086 ,  C23C14/087 ,  H01L21/02422 ,  H01L21/02579 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02631 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/94

Abstract: Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced.

Abstract translation: 提供一种使用p型氧化物半导体层的半导体器件及其制造方法。 该装置包括由至少一种氧化物形成的p型氧化物层，所述氧化物选自由含铜（Cu）的一氧化碳，含锡（Sn）的一氧化锡，含有Cu-Sn的铜锡氧化物 合金和含有Ni-Sn合金的镍锡氧化物。 因此，使用p型氧化物层容易显影透明或不透明的装置。 由于使用低温工艺形成的氧化物层被应用于半导体器件，所以可以简化半导体器件的制造工艺，并且可以降低制造成本。

公开(公告)号：US08030729B2

公开(公告)日：2011-10-04

申请号：US12243804

申请日：2008-10-01

Applicant: Nathaniel Quitoriano ,  Theodore I. Kamins

Inventor： Nathaniel Quitoriano ,  Theodore I. Kamins

IPC: H01L31/06

CPC classification number: H01L31/101 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/02617 ,  H01L21/02645 ,  H01L27/14647 ,  Y10S977/932 ,  Y10S977/95 ,  Y10S977/953

Abstract: A device disclosed herein includes a first layer, a second layer, and a first plurality of nanowires established between the first layer and the second layer. The first plurality of nanowires is formed of a first semiconductor material. The device further includes a third layer, and a second plurality of nanowires established between the second and third layers. The second plurality of nanowires is formed of a second semiconductor material having a bandgap that is the same as or different from a bandgap of the first semiconductor material.

Abstract translation: 本文公开的装置包括在第一层和第二层之间建立的第一层，第二层和第一多个纳米线。 第一多个纳米线由第一半导体材料形成。 该装置还包括第二层和第三层之间建立的第三层和第二组纳米线。 第二多个纳米线由具有与第一半导体材料的带隙相同或不同的带隙的第二半导体材料形成。

公开(公告)号：US07916987B2

公开(公告)日：2011-03-29

申请号：US12149969

申请日：2008-05-12

Applicant: Koichiro Tanaka ,  Hirotada Oishi

Inventor： Koichiro Tanaka ,  Hirotada Oishi

IPC: G02B6/12 ,  G02B6/26

CPC classification number: H01L21/02617 ,  G02B6/001 ,  G02B6/0048 ,  G02B6/0055 ,  G02B6/262 ,  G02B27/0927 ,  G02B27/095 ,  G02B27/0977 ,  G02B27/0994

Abstract: The present invention is to provide a beam homogenizer, a laser irradiation apparatus, and a method for manufacturing a semiconductor device, which can suppress the loss of a laser beam and form a beam spot having homogeneous energy distribution constantly on an irradiation surface without being affected by beam parameters of a laser beam. A deflector is provided at an entrance of an optical waveguide or a light pipe used for homogenizing a laser beam emitted from a laser oscillator. A pair of reflection planes of the deflector is provided so as to have a tilt angle to an optical axis of the laser beam, whereby the entrance of the optical waveguide or the light pipe is expanded. Accordingly, the loss of the laser beam can be suppressed. Moreover, by providing an angle adjusting mechanism to the deflector, a beam spot having homogeneous energy distribution can be formed at an exit of the optical waveguide.

Abstract translation: 本发明提供一种光束均化器，激光照射装置和半导体装置的制造方法，其能够抑制激光束的损失，并且在照射面上不间断地形成具有均匀的能量分布的束斑而不受影响 通过激光束的光束参数。 在用于使从激光振荡器发射的激光束均匀化的光波导或光管的入口处设置偏转器。 偏转器的一对反射面被设置为具有与激光束的光轴的倾斜角，从而扩大了光波导或光管的入射。 因此，可以抑制激光束的损失。 此外，通过向偏转器设置角度调节机构，可以在光波导的出口处形成具有均匀能量分布的束斑。

公开(公告)号：US20110045281A1

公开(公告)日：2011-02-24

申请号：US12860844

申请日：2010-08-20

Applicant: Rachael L. Myers-Ward ,  David Kurt Gaskill ,  Brenda L. VanMil ,  Robert E. Stahlbush ,  Charles R. Eddy, JR.

Inventor： Rachael L. Myers-Ward ,  David Kurt Gaskill ,  Brenda L. VanMil ,  Robert E. Stahlbush ,  Charles R. Eddy, JR.

IPC: C30B25/20 ,  B32B9/04 ,  B32B5/00 ,  C30B25/02 ,  C30B25/10

CPC classification number: C30B29/36 ,  C30B25/20 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02477 ,  H01L21/02529 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/30604 ,  H01L21/3065 ,  Y10T428/26

Abstract: A method for reducing/eliminating basal plane dislocations from SiC epilayers is disclosed. An article having: an off-axis SiC substrate having an off-axis angle of no more than 6°; and a SiC epitaxial layer grown on the substrate. The epitaxial layer has no more than 2 basal plane dislocations per cm2 at the surface of the epitaxial layer. A method of growing an epitaxial SiC layer on an off-axis SiC substrate by: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxially grow SiC on the substrate in the growth chamber. The substrate has an off-axis angle of no more than 6°. The growth conditions include: a growth temperature of 1530-1650° C.; a pressure of 50-125 mbar; a C/H gas flow ratio of 9.38×10−5-1.5×10−3; a C/Si ratio of 0.5-3; a carbon source gas flow rate during ramp to growth temperature from 0 to 15 sccm; and an electron or hole concentration of 1013-1019/cm3.

Abstract translation: 公开了一种减少/消除SiC外延层的基面位错的方法。 一种制品，具有：具有不大于6°的离轴角的离轴SiC衬底; 以及在衬底上生长的SiC外延层。 外延层在外延层的表面上每平方厘米不超过2个基面位错。 在离轴SiC衬底上生长外延SiC层的方法是：在生长条件下将硅源气体，碳源气体和载气流入生长室，以在生长室中的衬底上外延生长SiC 。 基板的离轴角度不大于6°。 生长条件包括：生长温度为1530-1650℃。 压力为50-125毫巴; C / H气体流量比为9.38×10-5-1.5×10-3; C / Si比为0.5-3; 斜坡期间的碳源气体流量从0到15sccm的生长温度; 电子或空穴浓度为1013-1019 / cm3。

公开(公告)号：US07892915B1

公开(公告)日：2011-02-22

申请号：US11367030

申请日：2006-03-02

Applicant: Jamal Ramdani ,  Craig Richard Printy ,  Thanas Budri

Inventor： Jamal Ramdani ,  Craig Richard Printy ,  Thanas Budri

IPC: H01L21/8249

CPC classification number: H01L29/7378 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02617

Abstract: A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosophorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles.

Abstract translation: 公开了一种用于高性能硅锗：具有磷光原子层掺杂（ALD）的碳（SiGe：C）基异质结双极晶体管（HBT））的基本结构。 ALD工艺使基底衬底受氮气（在大约等于500摄氏度的环境温度下），并提供另外的SiGe：C间隔层。 在ALD过程中，锗（Ge）和碳（C）的百分比浓度基本匹配，磷是优选的掺杂剂。 改进的SiGe：C HBT对工艺温度和曝光时间较不敏感，并且显示较低的掺杂剂偏析和更尖锐的基体分布。

公开(公告)号：US20100285639A1

公开(公告)日：2010-11-11

申请号：US12838683

申请日：2010-07-19

Applicant: Jorge Manuel Garcia ,  Loren N. Pfeiffer

Inventor： Jorge Manuel Garcia ,  Loren N. Pfeiffer

IPC: H01L21/335

CPC classification number: H01L29/78684 ,  C23C14/0605 ,  C23C14/5806 ,  C30B23/02 ,  C30B29/02 ,  H01L21/02376 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02527 ,  H01L21/02617 ,  H01L29/045 ,  H01L29/16 ,  H01L29/1606 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7781 ,  H01L29/78 ,  Y10T428/2982 ,  Y10T428/30

Abstract: A method includes an act of providing a crystalline substrate with a diamond-type lattice and an exposed substantially (111)-surface. The method also includes an act of forming a graphene layer or a graphene-like layer on the exposed substantially (111)-surface.

Abstract translation: 一种方法包括提供具有金刚石型晶格和暴露的基本上（111）表面的晶体衬底的动作。 该方法还包括在暴露的基本上（111）表面上形成石墨烯层或石墨烯层的动作。

公开(公告)号：US20100144121A1

公开(公告)日：2010-06-10

申请号：US12329279

申请日：2008-12-05

Applicant: Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

Inventor： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC: H01L21/20 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Abstract translation: 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US20070281156A1

公开(公告)日：2007-12-06

申请号：US11386080

申请日：2006-03-21

Applicant: Charles Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David Smith ,  Deli Wang ,  Zhaohui Zhong

Inventor： Charles Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David Smith ,  Deli Wang ,  Zhaohui Zhong

IPC: D02G3/00

CPC classification number: G11C13/025 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  C30B11/00 ,  C30B25/00 ,  C30B25/005 ,  C30B29/60 ,  C30B29/605 ,  G01N27/4146 ,  G01N33/54373 ,  G11C11/56 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/77 ,  G11C2213/81 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02603 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02645 ,  H01L21/02653 ,  H01L23/53276 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/267 ,  H01L29/73 ,  H01L29/7781 ,  H01L29/78696 ,  H01L29/861 ,  H01L29/868 ,  H01L31/0352 ,  H01L31/08 ,  H01L33/18 ,  H01L51/0048 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y02E10/549 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958 ,  Y10T428/2929 ,  Y10T428/298 ,  H01L2924/00

Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

公开(公告)号：US07301199B2

公开(公告)日：2007-11-27

申请号：US10196337

申请日：2002-07-16

Applicant: Charles M. Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln J. Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David C. Smith ,  Deli Wang ,  Zhaohui Zhong

Inventor： Charles M. Lieber ,  Xiangfeng Duan ,  Yi Cui ,  Yu Huang ,  Mark Gudiksen ,  Lincoln J. Lauhon ,  Jianfang Wang ,  Hongkun Park ,  Qingqiao Wei ,  Wenjie Liang ,  David C. Smith ,  Deli Wang ,  Zhaohui Zhong

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/06

CPC classification number: G11C13/025 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y30/00 ,  C30B11/00 ,  C30B25/00 ,  C30B25/005 ,  C30B29/60 ,  C30B29/605 ,  G01N27/4146 ,  G01N33/54373 ,  G11C11/56 ,  G11C13/0014 ,  G11C13/0019 ,  G11C13/04 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2213/77 ,  G11C2213/81 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02603 ,  H01L21/02617 ,  H01L21/02628 ,  H01L21/02645 ,  H01L21/02653 ,  H01L23/53276 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/267 ,  H01L29/73 ,  H01L29/7781 ,  H01L29/78696 ,  H01L29/861 ,  H01L29/868 ,  H01L31/0352 ,  H01L31/08 ,  H01L33/18 ,  H01L51/0048 ,  H01L51/0595 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/3011 ,  Y02E10/549 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/958 ,  Y10T428/2929 ,  Y10T428/298 ,  H01L2924/00

Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components. For example, semiconductor materials can be doped to form n-type and p-type semiconductor regions for making a variety of devices such as field effect transistors, bipolar transistors, complementary inverters, tunnel diodes, light emitting diodes, sensors, and the like.

Abstract translation: 本发明一般涉及亚微电子电路，更具体地涉及纳米尺度制品，包括可以在各种位置和各种级别选择性地掺杂的纳米线。 在一些情况下，制品可以是单晶。 纳米尺寸线可以例如沿其长度或径向掺杂，或者根据掺杂剂的掺杂剂浓度，掺杂剂的浓度或两者掺杂。 这可以用于在单个项目中提供n型和p型导电性，或者在彼此非常接近的不同项目中提供，例如在横杆阵列中。 描述了这种制品的制造和生长，以及这些制品的布置以制造电子，光电子或自旋电子器件和部件。 例如，可以掺杂半导体材料以形成n型和p型半导体区域，用于制造诸如场效应晶体管，双极晶体管，互补反相器，隧道二极管，发光二极管，传感器等的各种器件。

公开(公告)号：US20070148920A1

公开(公告)日：2007-06-28

申请号：US11643675

申请日：2006-12-22

Applicant: Hitoshi Kasai ,  Takuji Okahisa ,  Shunsuke Fujita ,  Naoki Matsumoto ,  Hideyuki Ijiri ,  Fumitaka Sato ,  Kensaku Motoki ,  Seiji Nakahata ,  Koji Uematsu ,  Ryu Hirota

Inventor： Hitoshi Kasai ,  Takuji Okahisa ,  Shunsuke Fujita ,  Naoki Matsumoto ,  Hideyuki Ijiri ,  Fumitaka Sato ,  Kensaku Motoki ,  Seiji Nakahata ,  Koji Uematsu ,  Ryu Hirota

IPC: H01L21/20 ,  C23C16/00

CPC classification number: H01L21/02617 ,  C23C16/303 ,  C23C16/4405 ,  C23C16/4488 ,  C30B23/02 ,  C30B25/02 ,  C30B29/403

Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.

Abstract translation: III族氮化物晶体物质的制造方法包括以下步骤：通过将HCl气体引入反应室来清洗反应室的内部，并将III族氮化物结晶物质气相沉积在清洁的反应室中。 III族氮化物晶体物质的制造装置包括将HCl气体引入反应室的结构，以及通过HVPE生长III族氮化物结晶物质的结构。 因此，提供了包括在晶体生长期间有效清洁附着在反应室内的沉积物的方法的III族氮化物晶体物质的制造方法以及制造方法中使用的制造装置。