公开(公告)号：US20010014962A1

公开(公告)日：2001-08-16

申请号：US09823564

申请日：2001-03-30

发明人： Kazuhisa Obuchi ,  Tetsuya Yano ,  Kazuo Kawabata ,  Takaharu Nakamura

IPC分类号： H03M013/03

CPC分类号： H03M13/2984 ,  H03M13/2707 ,  H03M13/275 ,  H03M13/2764 ,  H03M13/2767 ,  H03M13/2771 ,  H03M13/2782 ,  H03M13/2785 ,  H03M13/6505 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0071

摘要： In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) anda memory control unit (12) capable ofchanging data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.

摘要翻译： 在需要执行交织操作和解交织操作的Turbo解码装置等装置中，设置有存储单元（5）和能够改变数据写入顺序和数据读取顺序的存储器控​​制单元（12） 取决于数据是被交织还是去交织，到存储单元（5）。 通过这种布置，单个存储器单元（5）可以用作交织器和解交织器，从而减小设备的尺寸和成本。

公开(公告)号：US06192493B1

公开(公告)日：2001-02-20

申请号：US09000273

申请日：1998-01-27

申请人： Pierre Combelles ,  Damien Castelain ,  Denis Callonnec

发明人： Pierre Combelles ,  Damien Castelain ,  Denis Callonnec

IPC分类号： G06F1100

CPC分类号： H03M13/2785

摘要： To interleave or deinterleave data elements in first and second blocks transmitted alternately and each having N data elements with rank n lying between 0 and N−1, N being an integer, the data elements with ranks 0, . . . n, . . . N−1 in the first blocks are ordered in accordance with the successive ranks A(0), . . . A(n), . . . A(N−1) and the data elements with ranks 0, . . . n, . . . N−1 in the second block are ordered in accordance with the successive ranks A−1(0), . . . A−1(n), . . . A−1(N−1). A and A−1 are different functions such that A−1(A(n))=n.

摘要翻译： 为了交织或解交织交替发送的第一和第二块中的数据元素，并且每个具有N个数据元素，秩n位于0和N-1之间，N是整数，数据元素具有等级0。 。 。 n，。 。 。 第一个块中的N-1根据连续的等级A（0）排序。 。 。 A（n），。 。 。 A（N-1）和数据元素的等级为0，。 。 。 n，。 。 。 第二块中的N-1根据连续的等级A-1（0）来排序。 。 。 A-1（n），。 。 。 A-1（N-1）。 A和A-1是不同的功能，使得A-1（A（n））= n。

公开(公告)号：US5991857A

公开(公告)日：1999-11-23

申请号：US360612

申请日：1994-12-21

申请人： Anno J Koetje ,  Jukka Ranta ,  Alice Wilson

发明人： Anno J Koetje ,  Jukka Ranta ,  Alice Wilson

IPC分类号： H03M13/27 ,  H04B14/04 ,  H04L1/00 ,  H04Q7/38 ,  G06F12/02

CPC分类号： H04L1/0059 ,  H03M13/2764 ,  H03M13/2785 ,  H04L1/0043 ,  H04L1/0071

摘要： An interleaving process in which data is interleaved or interleaved data is de-interleaved. Input data units are distributed over a plurality of output groups of data units. In GSM telephony, input bits are distributed over nineteen transmission bursts. Incoming data units are written to a contiguous RAM and output groups are read from said RAM. Addressing circuitry controls the writing and reading to the RAM, such that data units are stored until required for an output group. After data has been read, these read locations are re-used for the storage of new input data, such that the duration over which a particular memory location stores a data unit depends upon the interleaving process delay for that particular data unit. The addressing circuitry includes modulo counters, each arranged to generate addressing signals for a respective set of memory locations within the RAM. Look-up tables are used to select modulo counts so as to provide conventional addresses to the RAM. In another embodiment block de-interleaving is performed during the writing of received bits to memory locations. However, said bits are written sequentially to said locations thereby allowing the remaining space to be used for other purposes. In particular, said space may be used for de-interleaving fast associated control channels etc. Bit position de-interleaving is then effected when the data is read from the memory locations or when read from intermediate frame buffer.

摘要翻译： 数据被交织或交织的数据被交织的交错处理。 输入数据单元分布在数据单元的多个输出组上。 在GSM电话中，输入位分布在十九个传输脉冲串上。 传入的数据单元被写入连续的RAM，并且从所述RAM读出输出组。 寻址电路控制对RAM的写入和读取，使得存储数据单元直到输出组需要。 在读取数据之后，这些读取位置被重新用于存储新的输入数据，使得特定存储器位置存储数据单元的持续时间取决于该特定数据单元的交织处理延迟。 寻址电路包括模计数器，每个计数器被布置成为RAM内的相应存储器单元集合生成寻址信号。 查询表用于选择模数，以便向RAM提供常规地址。 在另一个实施例中，在将接收到的比特写入存储器位置期间执行块去交织。 然而，所述位被顺序写入所述位置，从而允许剩余空间用于其他目的。 特别地，所述空间可以用于解交织快速相关联的控制信道等。然后当从存储器位置读取数据或者当从中间帧缓冲器读取数据时，进行位位置解交织。

公开(公告)号：US5572532A

公开(公告)日：1996-11-05

申请号：US315153

申请日：1994-09-29

申请人： Mark Fimoff ,  Scott F. Halozan ,  Raymond C. Hauge

发明人： Mark Fimoff ,  Scott F. Halozan ,  Raymond C. Hauge

IPC分类号： H03M13/27 ,  H04L27/00 ,  H04N19/89 ,  H03M13/22

CPC分类号： H03M13/2785 ,  H03M13/2732 ,  H03M13/276 ,  H04N19/89

摘要： A convolutional interleaver or deinterleaver comprises an address signal generator for repeatedly generating [(B-1)N/2]+1 sequences of address signals, where B is a desired interleave depth and N is a value equal to or greater than the number of data bytes in a R-S block of the data stream. Each of the sequences corresponds to a respective row of a B column matrix, the first column of which comprises [(B-1)N/2]+1 consecutively numbered values. Each remaining column comprises the preceding column rotated by an integer multiple of N/B. The address signals are applied to a memory having [(B-1)N/2]+1 storage locations for reading the data stored at the address memory location and then writing the current data byte to the same memory location.

摘要翻译： 卷积交织器或解交织器包括地址信号发生器，用于重复产生[（B-1）N / 2] +1个地址信号序列，其中B是期望的交织深度，N是等于或大于 数据流的RS块中的数据字节。 每个序列对应于B列矩阵的相应行，其第一列包括[（B-1）N / 2] +1个连续编号的值。 每个剩余的列包括以N / B的整数倍旋转的前一列。 地址信号被施加到具有[（B-1）N / 2] +1个存储位置的存储器，用于读取存储在地址存储器位置的数据，然后将当前数据字节写入相同的存储器位置。

公开(公告)号：US20180159791A1

公开(公告)日：2018-06-07

申请号：US15886068

申请日：2018-02-01

申请人： Panasonic Corporation

发明人： Peter Klenner

IPC分类号： H04L12/863 ,  H03M13/27 ,  H04L1/00

CPC分类号： H04L47/6245 ,  H03M13/27 ,  H03M13/271 ,  H03M13/2732 ,  H03M13/276 ,  H03M13/2785 ,  H03M13/2796 ,  H04L1/0071 ,  H04L1/0076 ,  H04L1/0085 ,  H04L47/6255

摘要： A convolutional interleaver included in a time interleaver, which performs convolutional interleaving includes: a first switch that switches a connection destination of an input of the convolutional interleaver to one end of one of a plurality of branches; a FIFO memories provided in some of the plurality of branches except one branch, wherein a number of FIFO memories is different among the plurality of branches; and a second switch that switches a connection destination of an output of the convolutional interleaver to another end of one of the plurality of branches. The first and second switches switch the connection destination when the plurality of cells as many as the codewords per frame have passed, by switching a corresponding branch of the connection destination sequentially and repeatedly among the plurality of branches.

公开(公告)号：US20180077447A1

公开(公告)日：2018-03-15

申请号：US15695345

申请日：2017-09-05

申请人： MStar Semiconductor, Inc.

发明人： CHUN-CHIEH WANG

IPC分类号： H04N21/4385 ,  H03M13/27 ,  H04N21/44 ,  H04N21/426 ,  H04N21/6402

CPC分类号： H04N21/4385 ,  G06F12/0607 ,  H03M13/2703 ,  H03M13/2735 ,  H03M13/2764 ,  H03M13/2782 ,  H03M13/2785 ,  H03M13/6552 ,  H04N21/426 ,  H04N21/42692 ,  H04N21/4382 ,  H04N21/44004 ,  H04N21/6402

摘要： A de-interleaving circuit that performs a time de-interleaving process on an interleaved block of an interleave signal includes: an input buffer, buffering multiple information units included in a time interleaved block; a writing address generator, generating multiple writing addresses according to a predetermined rule to write the information units buffered in the input buffer to a memory; a reading address generator, generating multiple reading addresses according to the predetermined rule to read the information units from the memory; and an output buffer, buffering the information units read from the memory. The information units are stored in multiple tiles of the memory. The tiles correspond to multiple regions of the time interleaved block, the multiple regions include a first region and a second region, and the dimensions of each tile in the first region are different from the dimensions of each tile in the second region.

公开(公告)号：US20170212682A1

公开(公告)日：2017-07-27

申请号：US15399120

申请日：2017-01-05

申请人： MStar Semiconductor, Inc.

发明人： CHUN-CHIEH WANG

IPC分类号： G06F3/06

CPC分类号： G06F3/064 ,  G06F3/0619 ,  G06F3/0659 ,  H03M13/2778 ,  H03M13/2785 ,  H04L1/0045 ,  H04L1/0052 ,  H04L1/0071

摘要： A time de-interleaving method is applied to a signal receiver of a communication system to perform a time de-interleaving process on an interleaved signal. The interleaved signal includes a first time interleaved block and a second time interleaved block. The time de-interleaving method includes: reading a first part of cells of the first time interleaved block from a memory; releasing a memory space corresponding to the first part of the cells in the memory; and writing a second part of cells of the second time interleaved block into the memory space before the first time interleaved block is completely read out from memory.

公开(公告)号：US20160140037A1

公开(公告)日：2016-05-19

申请号：US14939863

申请日：2015-11-12

申请人： iBiquity Digital Corporation

发明人： Marek Milbar

IPC分类号： G06F12/06 ,  H04B1/06 ,  H04W52/02 ,  H04L27/26

CPC分类号： G06F12/0607 ,  G06F2212/1028 ,  G06F2212/154 ,  G06F2212/174 ,  H03M13/2707 ,  H03M13/2785 ,  H03M13/6569 ,  H04B1/06 ,  H04H2201/18 ,  H04L27/2601 ,  H04L27/2649 ,  H04W52/0206 ,  Y02D70/164

摘要： A method of block deinterleaving data received at a digital radio broadcast receiver is described. The method includes providing a block of memory having a n×k addresses, wherein the block comprises a single table, receiving a digital radio broadcast signal at the receiver, and demodulating the digital radio broadcast signal into a plurality of interleaved data units. For at least one series of n×k data units a pointer step size is determined, and for each data unit in the series, an address in the block is calculated based on the pointer step size, and an output data unit is read from the block at the address, such that said output data units represent block deinterleaved data units. An input data unit from the plurality of interleaved data units is then written to the block at the address. Associated systems and computer readable storage media are presented.

摘要翻译： 描述了在数字无线电广播接收机处接收的数据块解交织数据的方法。 该方法包括提供具有n×k个地址的存储器块，其中该块包括单个表，在接收机处接收数字无线电广播信号，并将数字无线电广播信号解调为多个交错数据单元。 对于至少一系列n×k个数据单元，确定指针步长，并且对于串联中的每个数据单元，基于指针步长来计算块中的地址，并且从中读取输出数据单元 使得所述输出数据单元表示块去交织的数据单元。 然后，将来自多个交错数据单元的输入数据单元写入该地址处的块。 提出了相关系统和计算机可读存储介质。

公开(公告)号：US08433976B1

公开(公告)日：2013-04-30

申请号：US12768252

申请日：2010-04-27

申请人： Suleyman Sirri Demirsoy

发明人： Suleyman Sirri Demirsoy

IPC分类号： H03M13/00 ,  G11C29/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： H03M13/276 ,  H03M13/2707 ,  H03M13/2764 ,  H03M13/2785 ,  H03M13/6525

摘要： Interleaver designs and interleaving methods that perform block-wise interleaving by reading blocks into and out of memories, where a block can be written to the memory before another block has finished being read out of the memory, without data clashes, are provided. Corresponding deinterleavers and deinterleaving methods are disclosed.

摘要翻译： 交织器设计和交织方法通过将块读入和取出存储器来执行块式交织，其中在没有数据冲突的情况下，在存储器中读出另一个块已经结束之前可将块写入存储器。 公开了相应的解交织和解交织方法。

公开(公告)号：US08407561B2

公开(公告)日：2013-03-26

申请号：US13293231

申请日：2011-11-10

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： G11C29/00

CPC分类号： H03M13/2957 ,  H03M13/2757 ,  H03M13/2785 ,  H03M13/3972 ,  H03M13/6566 ,  H04L1/0071

摘要： Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, (MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (π) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors. This memory mapping allows collision-free reading and writing of updated information (as updated using parallel implemented turbo decoder) into memory banks.

摘要翻译： 具有二次多项式置换（QPP）交错的并行涡轮解码的公式灵活无冲突存储器存取。 提出了一种可以使用任何期望数量的并行实施的turbo解码处理器来执行已经使用QPP交织进行的turbo解码的装置。 呈现该方法以允许任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）在仍然使用QPP交织的所选实施例的情况下执行turbo编码信号的解码。 此外，无冲突存储器映射（MOD，C，W）提供了更多的自由度，用于选择满足具有任何所需数量的并行实现的turbo的并行turbo解码实现的特定二次多项式置换（QPP）交织（＆pgr） 解码处理器。 该存储器映射允许将更新的信息（使用并行实现的turbo解码器更新）的无冲突读写写入存储体。