公开(公告)号：US20020048329A1

公开(公告)日：2002-04-25

申请号：US09952210

申请日：2001-09-12

发明人： Hau Thien Tran ,  Kelly B. Cameron ,  Thomas A. Hughes

IPC分类号： H04L027/06

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for Min star calculations in a Map decoder. Min star calculations are performed by a circuit that includes a first circuit that performs an Min(A,B) operation simultaneously with a circuit that calculates a nulllog(1nullenullnullAnullBnull) value. The sign bit of the AnullB calculation is used to select whether A or B is a minimum. The AnullB calculation is also used to select either nulllog(1nullenullnullAnullBnull) or nulllog(1nullenullnullBnullAnull) as the correct calculation. In order to hasten the selection of either nulllog(1nullenullnullAnullBnull) or nulllog(1nullenullnullBnullAnull) as the correct calculation the apparatus does not wait for the AnullB calculation to complete. Any bit of the AnullB calculation between the third bit and final (sign bit) can be used for the selection. If an incorrect value is selected a log saturation circuit may correct the value. In addition an offset may be added nulllog(1nullenullnullAnullBnull) or nulllog(1nullenullnullBnullAnull) to assure that the calculation does not become negative, necessitating the use of an additional sign bit thereby increasing circuit complexity and slowing down the calculation. Additionally the log terms are computed based on a partial result of the AnullB calculation.

摘要翻译： 地图解码器中Min Star计算的方法和装置。 最小星号计算由包括与计算-log（1 + e- | A-B |）值的电路同时执行Min（A，B）操作的第一电路的电路执行。 A-B计算的符号位用于选择A或B是否为最小值。 A-B计算也用于选择-log（1 + e- | A-B |）或-log（1 + e- | B-A |）作为正确的计算。 为了加快-log（1 + e- | A-B |）或-log（1 + e- | B-A |）的选择作为正确的计算，装置不等待A-B计算完成。 第三位和第三位（符号位）之间的A-B计算的任何位都可用于选择。 如果选择了不正确的值，日志饱和电路可能会更正该值。 此外，可以添加一个偏移量-log（1 + e- | AB |）或-log（1 + e- | BA |），以确保计算不变为负值，从而需要使用附加符号位，从而增加 电路复杂度和计算速度减慢。 另外，基于A-B计算的部分结果来计算对数项。

公开(公告)号：US06360345B1

公开(公告)日：2002-03-19

申请号：US09364958

申请日：1999-07-30

申请人： Sang Wu Kim ,  Sung-Joon Park

发明人： Sang Wu Kim ,  Sung-Joon Park

IPC分类号： G06F1100

CPC分类号： H03M13/2978

摘要： In a turbo decoder for code rate 1/n which consists of a decoding block, that is, n−1 constituent decoders, n−2 interleavers and n−2 deinterleavers, one embodiment of a decoding method according to the present invention comprises: a first decoding process of sequentially decoding starting from a first constituent decoder among the n−1 constituent decoders to generate a first log-likelihood ratio; a second decoding process of sequentially decoding starting from a second constituent decoder to generate a second log-likelihood ratio different from the first log-likelihood ratio, the second decoding process being activated in parallel with the first decoding process; a (n−1)th decoding process of sequentially decoding starting from a (n−1)th constituent decoder to generate a (n−1)th log-likelihood ratio different from the log-likelihood ratios, the (n−1)th decoding process being activated in parallel with other decoding processes; a step of optimally weighting respective components forming each log-likelihood ratio simultaneously generated at each decoding process; and a step of combining the weighted log-likelihood ratios and performing the hard decision using a combiner to obtain diversity gain. Another embodiment of a decoding method comprises the steps of: after adding a decoding block, activating the decoding blocks in parallel; activating the constituent decoders of each decoding block in parallel; optimally weighting components of respective log-likelihood ratios from respective decoding processes and combining the weighted log-likelihood ratios at the combiner. The present invention considerably improves a bit error rate characteristic and reduces the number of iterations required to satisfy a given bit error rate, compared with the conventional decoding method.

摘要翻译： 在由解码块，即n-1个构成解码器，n-2个交织器和n-2个解交织器构成的码率为1 / n的turbo解码器中，根据本发明的解码方法的一个实施例包括： 在n-1个构成解码器之间从第一构成解码器开始依次解码的第一解码处理，以产生第一对数似然比; 从第二构成解码器开始顺序地解码以产生与第一对数似然比不同的第二对数似然比的第二解码处理，第二解码处理与第一解码处理并行地激活; 第（n-1）个解码处理，从第（n-1）个组成解码器开始顺序地解码，以产生与对数似然比不同的第（n-1）个对数似然比，所述第（n-1） 解码过程与其他解码过程并行激活; 在每个解码过程中同时产生形成每个对数似然比的各个分量的最佳加权的步骤; 以及组合加权对数似然比并使用组合器执行硬判决以获得分集增益的步骤。 解码方法的另一实施例包括以下步骤：在添加解码块之后并行激活解码块; 激活每个解码块的组成解码器并行; 从相应的解码过程对各个对数似然比的分量进行最佳加权，并组合在组合器处的加权对数似然比。 与常规解码方法相比，本发明显着地提高了比特误码率特性并减少了满足给定比特误码率所需的迭代次数。

公开(公告)号：US20170279468A1

公开(公告)日：2017-09-28

申请号：US15460155

申请日：2017-03-15

申请人： SK Hynix Inc.

发明人： Naveen Kumar ,  Aman Bhatia ,  Yi-Min Lin

IPC分类号： H03M13/45 ,  H03M13/00 ,  H03M13/29

CPC分类号： H03M13/6502 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2942 ,  H03M13/2963 ,  H03M13/2978 ,  H03M13/453

摘要： A memory device includes a memory array, a processor, and a decoding apparatus. The processor is coupled to the memory array and configured to read encoded data from the memory array. The encoded data includes a plurality of data blocks and each data block is included in two or more data codewords. Further, data codewords belonging to a same pair of data codewords share a common data block. The decoding apparatus is configured to iteratively decode data codewords using hard decoding and soft decoding, and to correct stuck errors by identifying failed data blocks based on shared blocks between failed data codewords.

公开(公告)号：US20160149596A1

公开(公告)日：2016-05-26

申请号：US14555309

申请日：2014-11-26

申请人： Freescale Semiconductor, Inc.

发明人： Robert Bahary ,  Eric J. Jackowski

IPC分类号： H03M13/29 ,  H03M13/45 ,  G06F11/10

CPC分类号： H03M13/2957 ,  G06F11/1076 ,  H03M13/2978 ,  H03M13/6505 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6566

摘要： A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates LLRs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. The turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle. The data can be rearranged within the words in an order format for the turbo decoder engines to later read them by providing sub-words corresponding to respective ones of the plurality of turbo decoder engines.

摘要翻译： turbo解码器以已知的方式存储系统存储器和奇偶校验存储器中的接收数据，该方法将被用于被并行操作的Turbo解码器引擎的后续迭代。 加载器将LLR接收并分离为系统和奇偶校验数据，并将它们存储到每个周期的单词的一部分中，直到在系统存储器和奇偶校验存储器中相应的一个字中的字满。 turbo解码器引擎在单个周期中从系统存储器的一个字和奇偶校验存储器的一个字读取LLR。 数据可以按照订单格式在单词内重新排列，以便turbo解码器引擎稍后通过提供与多个turbo解码器引擎中的相应的turbo解码器引擎相对应的子字来读取它们。

公开(公告)号：US09350389B2

公开(公告)日：2016-05-24

申请号：US13933734

申请日：2013-07-02

申请人： Broadcom Corporation

发明人： Wei-Min Zhang ,  Timothy A. Misko

IPC分类号： H03M13/29 ,  H04L1/00 ,  H04L25/14

CPC分类号： H03M13/29 ,  H03M13/2978 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0076 ,  H04L25/14

摘要： Error correction coding across multiple channels is provided in multi-channel transmission systems. Specifically, redundancy is provided by selecting a portion of original data from each of a plurality of original channels, performing at least one encoding operation using the portions of original data to produce at least one portion of redundancy data, including the portion of redundancy data in at least one redundancy channel, and transmitting the redundancy channel along with the original channels. Error correction is achieved by receiving at least one redundancy channel and a plurality of original channels, selecting a portion of redundancy data from the redundancy channel, selecting a portion of original data from each of the original channels, and performing at least one decoding operation using the portion of redundancy data and the portions of original data to correct at least one error in the portions of original data.

公开(公告)号：US08559451B2

公开(公告)日：2013-10-15

申请号：US12037573

申请日：2008-02-26

申请人： Udi Shtalrid

发明人： Udi Shtalrid

IPC分类号： H04L12/28

CPC分类号： H03M13/2978 ,  H03M13/2775 ,  H03M13/6525 ,  H03M13/653 ,  H03M13/6536 ,  H03M13/6561 ,  H03M13/6566

摘要： A turbo decoder has at least two Bahl, Cocke, Jelinek, and Raviv (BCJR) processors in parallel, each in serial communication with respective interleavers. The BCJR processors and interleavers are in communication with a memory module that is internally split into non-overlapping memory banks. The turbo decoder includes respective sorter circuits in communication with the output of each BCJR processor/interleaver. A sorter circuit receives a data block from a BCJR processor/interleaver and directs the data block to the memory bank designated by an address assigned to the data block by an interleaver.

摘要翻译： turbo解码器具有并行的至少两个Bahl，Cocke，Jelinek和Raviv（BCJR）处理器，每个处理器与相应的交织器串行通信。 BCJR处理器和交织器与内部分为非重叠存储器组的存储器模块进行通信。 turbo解码器包括与每个BCJR处理器/交织器的输出通信的各个分类器电路。 分拣机电路从BCJR处理器/交织器接收数据块，并将数据块引导到由交织器分配给数据块的地址指定的存储体。

公开(公告)号：US20120326898A1

公开(公告)日：2012-12-27

申请号：US12224496

申请日：2006-12-12

申请人： Martin Bossert ,  Axel Hof ,  Martin Weckerle

发明人： Martin Bossert ,  Axel Hof ,  Martin Weckerle

IPC分类号： H03M5/00

CPC分类号： H03M13/3746 ,  H03M13/23 ,  H03M13/256 ,  H03M13/258 ,  H03M13/296 ,  H03M13/2978

摘要： A method codes information, wherein bits that are to be coded are divided into successive first blocks. Second blocks are determined, respectively, by applying a permutation to each of the first blocks. Third blocks are determined by interleaving each of the first blocks with a respective second block. The third blocks are convolution coded, and the bits are combined to form symbols according to the convolutional code. There is a related method for decoding and devices for carrying out the methods.

摘要翻译： 一种方法编码信息，其中要编码的比特被分成连续的第一块。 分别通过对每个第一块应用置换来确定第二块。 通过用相应的第二块交织每个第一块来确定第三块。 第三块被卷积编码，并且这些比特被组合以根据卷积码形成符号。 存在用于解码的相关方法和用于执行该方法的装置。

公开(公告)号：US08301983B2

公开(公告)日：2012-10-30

申请号：US11992802

申请日：2005-09-30

申请人： Andrey Gennadievich Efimov ,  Andrey Vladimirovich Belogolovy

发明人： Andrey Gennadievich Efimov ,  Andrey Vladimirovich Belogolovy

IPC分类号： G06F11/00

CPC分类号： H03M13/296 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/2978 ,  H03M13/6502

摘要： Apparatus and methods are provided to decode signals from a communication channel to reconstruct transmitted information. Embodiments may include applying a plurality of decoders to a code, in which reliability values are provided to a decoder such that the decoder receives the reliability values determined by and provided from only one other decoder of the plurality of decoders. A valid codeword may be output from application of the plurality of decoders to the code.

摘要翻译： 提供装置和方法来解码来自通信信道的信号以重建发送的信息。 实施例可以包括将多个解码器应用于代码，其中将可靠性值提供给解码器，使得解码器接收由多个解码器中的另一个解码器确定并由其提供的可靠性值。 可以从多个解码器的应用程序向代码输出有效的码字。

公开(公告)号：US08065587B2

公开(公告)日：2011-11-22

申请号：US11811013

申请日：2007-06-07

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2978 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/6516 ,  H03M13/6525 ,  H03M13/6561

摘要： Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits. This approach also is directly adaptable to parallel turbo decoding, in which any desired degree of parallelism can be employed. Alternatively, as few as one turbo decoder can be employed in a fully non-parallel implementation as well. Also, this approach allows for storage of a reduced number of parameters to accommodate a wide variety of interleaves.

摘要翻译： 降低复杂度ARP（几乎规则排列）交错，提供适应任何可能的turbo码块大小的灵活的粒度和并行性。 提出了一种新颖的方法，当仅需要非常少量的虚拟位时，可以采用任何期望的turbo码块大小。 这种方法也可直接适用于平行turbo解码，其中可以采用任何期望的并行度。 或者，也可以在完全非并行实现中使用少至一个turbo解码器。 此外，该方法允许存储少量参数以适应各种各样的交错。

公开(公告)号：US08009769B2

公开(公告)日：2011-08-30

申请号：US11885978

申请日：2006-03-10

申请人： Matthieu Arzel ,  Fabrice Seguin ,  Cyril Lahuec

发明人： Matthieu Arzel ,  Fabrice Seguin ,  Cyril Lahuec

IPC分类号： H04L27/06

CPC分类号： H03M13/2978 ,  H03M13/23 ,  H03M13/27 ,  H03M13/6597

摘要： A method and a device (20) for decoding a frame capable of being split into p sub-frames each consisting of k information symbols, a first n−k redundant symbols and a last n−k redundant symbols. The decoding process uses two individual decoders (21, 23) which concurrently produce extrinsic data (Extr1i, Extr2i) respectively concerning information symbols and interleaved information symbols. The values of the extrinsic data (Extr1i, Extr2i) are refined by cross-feedback of said data to the input of the decoders (21, 23).

摘要翻译： 一种用于对能够被分割成p个子帧的帧进行解码的方法和装置（20），每个子帧由k个信息符号，第一n-k个冗余符号和最后n个k个冗余符号组成。 解码过程使用分别同时产生关于信息符号和交织的信息符号的外在数据（Extr1i，Extr2i）的两个单独的解码器（21,23）。 外部数据（Extr1i，Extr2i）的值通过所述数据的交叉反馈来精确地解码器（21,23）的输入。