摘要:
A modular expandable telecommunication system having a main cabinet and at least one expansion cabinet that are interconnected with each other to obtain an extended telecommunication system with increased connection possibilities for extensions and trunks. The main cabinet and each expansion cabinet have a transmission interface unit allowing connection of the expansion cabinet(s) to the main cabinet via a single transmission link conveying voice/data channels and low level signaling for mutual synchronization and clock recovery for all interconnected cabinets. The main cabinet has a master clock device, a CPU for running software applications and a DSP for routing the higher level messages issued by the CPU depending on the physical location of the expansion cabinet.
摘要:
A method for multi-path TDM data transmission includes: applying a plurality of high-speed serial lines to connect a center switch network board to a plurality of service boards; multiplexing multi-path TDM data from the center switch network board at transmitting side, and transmitting TDM data multiplexed in batch via one of the high-speed serial lines to one of the service boards; at receiving side, serial receiving the TDM data multiplexed and de-multiplexing the TDM data multiplexed to multiple TDM paths. The TDM bridge connector includes: a TDM high-speed serial transmitting adaptive circuit, and a TDM high-speed serial receiving adaptive circuit and a clock control circuit. The invention increases greatly transmission capacity and looses the requirement of clock synchronization, so the system reliability is greatly raised.
摘要:
A forwarding unit such as a DSLAM (8) receives (21) Ethernet packets and forwards information therein on digital subscriber lines (27). For forwarding voice information of received Ethernet packets a reference clock signal is generated by a clock device (28) and provided to modems (23) for the digital subscriber lines. The clock device includes an extraction unit (29) for selecting at least one stream of received Ethernet packets, and a clock signal generating unit, configured as an adaptive clock unit (31), for generating a reference clock signal according to arrival times of packet in selected packet stream or streams. The reference clock signal can be provided to time reference units (25) in the modems. The extraction unit can analyze received Ethernet packets to find streams of packets from one destination to one user, the packets of each of the streams carrying real time information belonging to a real time service and then select one or more streams to be used by the adaptive clock unit.
摘要:
A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.
摘要:
A technique for embedding a first clock phase within a second signal is described. In one embodiment, the invention comprises a method of embedding a phase of a first signal within a second signal comprising the steps of monitoring a first signal for a frame event, responsive to detection of a frame event in the first clock signal, determining a position of the frame event relative to a current segment of a second signal, and embedding in the current segment of the second signal a value representative of the relative position of the detected frame event.
摘要:
A system for automating cross connections in an access network. The automated cross connect system comprises of a plurality of upstream line interface circuits adapted for connection to upstream communication links, and a plurality of downstream line interface circuits adapted for connection to downstream communication links. The upstream and downstream line interface circuits are interconnected by an automated cross connect switch that selectively couples particular upstream line interface circuits to particular downstream line interface circuits, in response to routing commands sent from a command center. Thus, the automated cross connect system selectively establishes a bi-directional communication path between the upstream line interface circuits and the downstream line interface circuits, thereby providing a communication path between a selected upstream communication link and downstream communication link. The automated cross connect switch may be implemented in either a space or time multiplexing devices, such as a physical layer router, which comprises an array of cross connected multiplexers, or a time domain multiplexer switch, which composes an array of serializers connected to a time division multiplexed bus.
摘要:
Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.
摘要:
In an audio-digital telephone interface system, selective operation prompts a caller with oral instructions to provide: digital control signals, digital data signals (numeric) or audio signals. Inbound and outbound operations are involved and inbound callers are qualified as by automatic number identification (ANI) signals and consumable key operation. A data cell is loaded in accordance with an operating program and the resulting data packet is flagged depending on the presence of audio signals. Data packets are returned to storage, as for subsequent addressing to call up, as to process or cue a caller. The illustrative format receives and organizes order data for goods or services or to isolate a subset or a sub-subset of callers.
摘要:
Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
摘要:
A multi-stage clock distribution scheme for use in a signaling server organized into a plurality of uniquely addressable shelves. The signaling server includes a system timing generator, one or more clock distribution modules arranged in a nested hierarchical manner, and a plurality of bus control modules, wherein each bus control module interfaces with at least a portion of line cards disposed in a shelf. The system timing generator provides a framed serial control signal, SFI, for controlling the operation of the multi-stage clock distribution scheme. The SFI signal encodes the IDs of the clock distribution modules and bus control modules whereby a system clock generated by the system timing generator based on a select reference input is successively fanned-out by the intermediate clock distribution modules based on address and ID information encoded in select fields of the SFI frames until the fanned-out system clocks are received by the bus control modules. Thereafter, each bus control module provides a copy of the system clock to the line cards controlled by it based on the SFI signal.