公开(公告)号：US20220399236A1

公开(公告)日：2022-12-15

申请号：US17342935

申请日：2021-06-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Wagno Alves Braganca, JR. ,  KyungOe Kim

IPC: H01L21/66 ,  H01L23/00 ,  G06T7/13 ,  G06T7/136 ,  H04N5/33

Abstract: A semiconductor device is formed by providing a semiconductor die. A laser-assisted bonding (LAB) assembly is disposed over the semiconductor die. The LAB assembly includes an infrared (IR) camera. The IR camera is used to capture an image of the semiconductor die. Image processing is performed on the image to identify corners of the semiconductor die. Regions of interest (ROI) are identified in the image relative to the corners of the semiconductor die. Parameters can be used to control the size and location of the ROI relative to the respective corners. The ROI are monitored for temperature using the IR camera while LAB is performed.

公开(公告)号：US20220365436A1

公开(公告)日：2022-11-17

申请号：US17319785

申请日：2021-05-13

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Giwoong Nam ,  Junghwan Jang ,  Inhee Hwang ,  Taekyu Choi ,  Sanghyun Park

IPC: G03F7/16 ,  H01L21/02

Abstract: A semiconductor manufacturing device has an outer cup and inner cup with a wafer suction mount disposed within the outer cup. A photoresist material is applied to a first surface of a semiconductor wafer disposed on the wafer suction mount while rotating at a first speed. A gas port is disposed on the inner cup for dispensing a gas oriented toward a bottom side of the semiconductor wafer. The gas port purges a second surface of the semiconductor wafer with a gas to remove contamination. The second surface of the semiconductor wafer is rinsed while purging with the gas. The gas can be a stable or inert gas, such as nitrogen. The contamination is removed from the second surface of the semiconductor wafer through an outlet between the inner cup and outer cup. The semiconductor wafer rotates at a second greater speed after discontinuing purge with the gas.

公开(公告)号：US11488838B2

公开(公告)日：2022-11-01

申请号：US16918643

申请日：2020-07-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

公开(公告)号：US20220246541A1

公开(公告)日：2022-08-04

申请号：US17660093

申请日：2022-04-21

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： SungWon Cho ,  ChangOh Kim ,  Il Kwon Shim ,  InSang Yoon ,  KyoungHee Park

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/36 ,  H01L23/522 ,  H01L23/50 ,  H01L23/60 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31 ,  H01L23/367

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. An encapsulant is deposited over the semiconductor die and substrate with a surface of the semiconductor die exposed from the encapsulant. A first shielding layer is formed over the semiconductor die. In some embodiments, the first shielding layer includes a stainless steel layer in contact with the surface of the semiconductor die and a copper layer formed over the stainless steel layer. The first shielding layer may further include a protective layer formed over the copper layer. One embodiment has a heatsink bonded to the semiconductor die through a solder layer. A second shielding layer can be formed over a side surface of the semiconductor die.

公开(公告)号：US20220199423A1

公开(公告)日：2022-06-23

申请号：US17127079

申请日：2020-12-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoungHee Park ,  JinHee Jung ,  OMin Kwon ,  JiWon Lee ,  YuJeong Jang

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/544 ,  H01L23/552 ,  H01L21/683

Abstract: A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

公开(公告)号：US11342294B2

公开(公告)日：2022-05-24

申请号：US16821093

申请日：2020-03-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  HunTeak Lee ,  OhHan Kim ,  HeeSoo Lee ,  DaeHyeok Ha ,  Wanil Lee

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component.

公开(公告)号：US11088082B2

公开(公告)日：2021-08-10

申请号：US16116485

申请日：2018-08-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Changoh Kim ,  Kyounghee Park ,  Kyowang Koo ,  Sungwon Cho

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/04 ,  H01L25/065 ,  H01L21/78 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor device has a substrate. A lid is disposed over the substrate. An encapsulant is deposited over the substrate. A film mask is disposed over the encapsulant with the lid exposed from the film mask and encapsulant. A conductive layer is formed over the film mask, encapsulant, and lid. The film mask is removed after forming the conductive layer.

公开(公告)号：US20210225778A1

公开(公告)日：2021-07-22

申请号：US17032005

申请日：2020-09-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YoungCheol Kim ,  ChoonHeung Lee ,  WonGyou Kim

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device has a substrate and a plurality of bond wires is disposed in a pattern across on the substrate. The pattern of bond wires can be a plurality of rows of bond wires. A plurality of electrical components is disposed over the substrate as an SIP module. An encapsulant is deposited over the substrate, electrical components, and bond wire. An opening is formed in the encapsulant extending to the bond wire. The opening can be a trench extending across the bond wires disposed on the substrate, or a plurality of openings individually exposing each of a plurality of bond wires. A conductive material is disposed in the opening. A shielding layer is formed over the encapsulant and in contact with the conductive material. The shielding layer, conductive material, and bond wires reduce the effects of EMI, RFI, and other inter-device interference.

公开(公告)号：US20210210437A1

公开(公告)日：2021-07-08

申请号：US17205779

申请日：2021-03-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  KyoWang Koo ,  SungWon Cho ,  BongWoo Choi

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01R43/20 ,  H01R43/26 ,  H01R12/79 ,  H01R12/52

Abstract: A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shielding layer is formed over the encapsulant and terminal. A portion of the shielding layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shielding layer and the portion of the insulating layer can be removed by laser ablation.

公开(公告)号：US11011423B2

公开(公告)日：2021-05-18

申请号：US16204737

申请日：2018-11-29

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Thomas J. Strothmann ,  Damien M. Pricolo ,  Il Kwon Shim ,  Yaojian Lin ,  Heinz-Peter Wirtz ,  Seung Wook Yoon ,  Pandi C. Marimuthu

IPC: H01L23/522 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L21/683

Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.