公开(公告)号：US07612638B2

公开(公告)日：2009-11-03

申请号：US11486903

申请日：2006-07-14

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H01P3/00 ,  H01P3/12 ,  H01P3/14 ,  H01P1/00 ,  H01P1/06

CPC分类号： H01P3/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.

摘要翻译： 公开了一种半导体集成电路中的波导，波导包括水平的第一金属板，在第一金属板上方的水平的第二金属板，由绝缘材料隔开，并且多个金属通孔位于两条平行的线上，垂直延伸穿过 所述绝缘材料与所述第一和第二金属板两者接触，其中所述第一和第二金属板和所述多个金属通孔以横截面视图形成可用作波导的金属外壳。

公开(公告)号：US20090002058A1

公开(公告)日：2009-01-01

申请号：US11769611

申请日：2007-06-27

申请人： Po Yao Ker ,  Shine Chung ,  Fu-Lung Hsueh

发明人： Po Yao Ker ,  Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H01H37/76 ,  G11C5/14

CPC分类号： G11C17/18 ,  G11C5/147

摘要： The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory.

摘要翻译： 本发明公开了一种用于感测放大器的偏置电路，其具有被感测的器件，该感测器件处于非编程状态和编程状态，该偏置电路包括至少一个第一分支，该第一分支具有至少一个基本上形成 与感测下的设备相同并且保持在未编程状态，并且至少一个第二设备形成也与感测下的设备基本相同并处于编程状态，其中至少一个第一设备和至少一个 第二设备串联连接。 本发明的典型应用是电熔丝存储器。

公开(公告)号：US07394637B2

公开(公告)日：2008-07-01

申请号：US11304174

申请日：2005-12-15

申请人： Sung-Chieh Lin ,  Hung-Jen Liao ,  Fu-Lung Hsueh ,  Jiann-Tseng Huang

发明人： Sung-Chieh Lin ,  Hung-Jen Liao ,  Fu-Lung Hsueh ,  Jiann-Tseng Huang

IPC分类号： H02H5/04

CPC分类号： G11C17/18

摘要： A sense amplifier for detecting a logic state of a selected electrical fuse cell among a number of unselected electrical fuse cells includes a bias module coupled to a power supply for generating a first current, and a tracking module coupled to the bias module for generating a second current. A current supplier is coupled to the bias module and the tracking module for generating a third current substantially equal to a sum of the first and second currents scaled by a predetermined factor, the third current being diverted into a first sub-current flowing through the selected electrical fuse cell and a second sub-current leaking through the unselected electrical fuse cells. The tracking module is so configured that the second current scaled by the predetermined factor is substantially equal to the second sub-current, thereby avoiding the first sub-current to be reduced by the second sub-current.

摘要翻译： 用于检测多个未选择的电熔丝单元中的所选择的电熔丝单元的逻辑状态的读出放大器包括耦合到电源的用于产生第一电流的偏置模块，以及耦合到偏置模块的跟踪模块，用于产生第二 当前。 当前供应商耦合到偏置模块和跟踪模块，用于产生基本上等于由预定因子缩放的第一和第二电流之和的第三电流，第三电流被转移到流过所选择的第一电流的第一子电流 电熔丝单元和第二子电流通过未选择的电熔丝单元泄漏。 跟踪模块被配置为使得按预定因子缩放的第二电流基本上等于第二子电流，从而避免第一子电流被第二子电流减小。

公开(公告)号：US09524934B2

公开(公告)日：2016-12-20

申请号：US13302335

申请日：2011-11-22

申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Kuoyuan (Peter) Hsu

发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Kuoyuan (Peter) Hsu

IPC分类号： H01L21/8238 ,  H01L23/525 ,  H01L27/06 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L23/5256 ,  H01L21/823437 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.

摘要翻译： 形成集成电路的方法包括在衬底上形成至少一个晶体管。 形成至少一个晶体管包括在衬底上形成栅极电介质结构。 在栅介电结构上形成功函数金属层。 在功函数金属层上形成导电层。 源极/漏极（S / D）区域形成为与栅极电介质结构的每个侧壁相邻。 在衬底上形成至少一个电熔丝。 形成至少一个电熔丝包括在衬底上形成第一半导体层。 在第一半导体层上形成第一硅化物层。

公开(公告)号：US09129940B2

公开(公告)日：2015-09-08

申请号：US13419911

申请日：2012-03-14

申请人： Hsieh-Hung Hsieh ,  Yi-Hsuan Liu ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Hsieh-Hung Hsieh ,  Yi-Hsuan Liu ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： G01R35/00 ,  H01L23/48 ,  H01L23/66 ,  H01L25/065 ,  H04B5/00

CPC分类号： H01L23/48 ,  H01L23/66 ,  H01L25/0657 ,  H01L2225/06531 ,  H01L2924/0002 ,  H04B5/0075 ,  H01L2924/00

摘要： An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils.

摘要翻译： 集成电路包括在垂直堆叠中耦合到第一芯片的第一芯片和第二芯片。 第一芯片包括射频电路和电耦合到射频电路的第一线圈。 第二芯片包括校准电路和电耦合到校准电路的第二线圈。 校准电路被配置为通过第一和第二线圈之间的感应耦合来校准设置在第一芯片上的射频电路。

公开(公告)号：US08957482B2

公开(公告)日：2015-02-17

申请号：US12731325

申请日：2010-03-25

申请人： Fu-Lung Hsueh ,  Tao Wen Chung ,  Po-Yao Ke ,  Shine Chung

发明人： Fu-Lung Hsueh ,  Tao Wen Chung ,  Po-Yao Ke ,  Shine Chung

IPC分类号： H01L23/62 ,  H01L27/06 ,  H01L23/525 ,  H01L27/112 ,  H01L27/10 ,  H01L29/78

CPC分类号： H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In various embodiments, the fuse is formed from silicide and on top of a fin of a fin structure. Because the fuse is formed on top of a fin, its width takes the width of the fin, which is very thin. Depending on implementations, the fuse is also formed using planar technology and includes a thin width. Because the width of the fuse is relatively thin, a predetermined current can reliably cause the fuse to be opened. Further, the fuse can be used with a transistor to form a memory cell used in memory arrays, and the transistor utilizes FinFET technology.

摘要翻译： 在各种实施例中，熔丝由硅化物形成，并且在翅片结构的翅片的顶部上形成。 因为熔丝形成在翅片的顶部，所以它的宽度取得了非常薄的翅片的宽度。 根据实施方案，保险丝也使用平面技术形成并且包括薄的宽度。 因为保险丝的宽度较薄，所以能够可靠地使保险丝断开。 此外，熔丝可以与晶体管一起使用以形成用于存储器阵列的存储单元，并且晶体管利用FinFET技术。

公开(公告)号：US08760255B2

公开(公告)日：2014-06-24

申请号：US13206584

申请日：2011-08-10

申请人： Ping-Lin Yang ,  Jun-De Jin ,  Fu-Lung Hsueh ,  Sa-Lly Liu ,  Tong-Chern Ong ,  Chun-Jung Lin ,  Ya-Chen Kao

发明人： Ping-Lin Yang ,  Jun-De Jin ,  Fu-Lung Hsueh ,  Sa-Lly Liu ,  Tong-Chern Ong ,  Chun-Jung Lin ,  Ya-Chen Kao

IPC分类号： H01F5/00

CPC分类号： H01L25/0657 ,  H01F5/00 ,  H01F27/2804 ,  H01F41/046 ,  H01F2027/2809 ,  H01L23/48 ,  H01L23/5227 ,  H01L2225/06531 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

摘要： A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

摘要翻译： 通信结构包括具有第一线圈的第一半导体衬底和在第一半导体衬底上方具有第二线圈的第二半导体衬底。 第一和第二线圈的内边缘限定在第一线圈下方延伸并在第二线圈之上的体积的边界。 铁磁芯至少部分地位于边界内，使得在第一和第二线圈之间提供互感以在第一和第二线圈之间无线地传输信号或电力。

公开(公告)号：US08661389B2

公开(公告)日：2014-02-25

申请号：US13084748

申请日：2011-04-12

申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Li-Chun Tien

发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Li-Chun Tien

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of designing an integrated circuit includes providing a cell library including a first and second cell structures. The cell structures each include a dummy gate electrode disposed on a boundary. An edge gate electrode is disposed adjacent to the dummy gate electrode. An oxide definition (OD) region has an edge disposed between the edge gate electrode and the dummy gate electrode. The method includes determining if the cell structures are to be abutted with each other. If so, the method includes abutting the cell structures. If not so, the method includes increasing areas of portions of the OD regions between the edge gate electrodes and the dummy gate electrodes.

摘要翻译： 设计集成电路的方法包括提供包括第一和第二单元结构的单元库。 电池结构各自包括设置在边界上的虚拟栅电极。 边缘栅电极被设置成与虚拟栅电极相邻。 氧化物定义（OD）区域具有设置在边缘栅电极和伪栅电极之间的边缘。 该方法包括确定单元结构是否彼此邻接。 如果是，则该方法包括邻接单元结构。 如果不是这样，则该方法包括增加边缘栅极电极和虚拟栅电极之间的OD区域的部分区域。

公开(公告)号：US20140049329A1

公开(公告)日：2014-02-20

申请号：US13586033

申请日：2012-08-15

申请人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

发明人： Yen-Jen Chen ,  I-Ting Lee ,  Hsieh-Hung Hsieh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh ,  Shen-Luan Liu

IPC分类号： H03L7/099

CPC分类号： H03K3/0322 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/087 ,  H03L7/089 ,  H03L7/099

摘要： One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.

摘要翻译： 本文提供了一种用于无分频锁相环（PLL）和相关相位检测器（PD）的技术和系统。 在一些实施例中，接收脉冲相位检测器（pulsePD）信号，压控振荡器正差分（VCOP）信号和压控振荡器负差分（VCON）信号。 基于pulsePD信号，VCOP信号和VCON信号产生用于第一电荷泵（CP）的上升信号和下降信号以及用于第二CP的上升信号和下降信号。 例如，生成CP信号以分别控制第一CP和第二CP。 在一些实施例中，产生CP信号，使得CP有助于调整相对于pulsePD信号的VCON和VCOP信号的零交叉相位。 以这种方式，提供无分频PLL，从而减轻PLL功耗。

公开(公告)号：US08476972B2

公开(公告)日：2013-07-02

申请号：US12813620

申请日：2010-06-11

申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： G06G7/12 ,  G06G7/26

CPC分类号： G04F10/005

摘要： A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

摘要翻译： 时间放大器电路具有第一和第二反相器以及第一和第二下拉通路。 每个反相器包括第一NMOS晶体管和第一PMOS晶体管。 第一NMOS晶体管的源极直接或通过具有耦合到相应输入节点的栅极的第一附加NMOS晶体管耦合到接地节点。 第一和第二反相器分别耦合到第一和第二输入节点以及第一和第二输出节点。 第一下拉路径从第一输出节点到接地节点，并且响应于第一输入信号而使第二输出信号为高。 第二下拉路径从第二输出节点到地，并且响应于第二输入信号并且第一输出信号为高而使能。