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271 条记录 (耗时 0.018 秒)

    Control Loop Management and Vector Signalling Code Communications Links
    41.
    发明申请
    Control Loop Management and Vector Signalling Code Communications Links 有权
    控制环路管理和矢量信令码通信链路

    公开(公告)号：US20150256326A1

    公开(公告)日：2015-09-10

    申请号：US14717717

    申请日：2015-05-20

    申请人： Kandou Labs S.A.

    发明人： Richard Simpson ,  Roger Ulrich

    IPC分类号： H04L7/00 ,  H04L1/00

    CPC分类号： H04L7/0025 ,  H03L7/0807 ,  H04L1/0001 ,  H04L1/0042 ,  H04L1/0045 ,  H04L1/0057 ,  H04L7/00 ,  H04L7/0334 ,  H04L25/0272 ,  H04L25/03 ,  H04L2001/0094

    摘要： Vector signaling code communications systems rely on group transmission of code symbols using multiple signaling channels that must be actively monitored and adjusted to minimize differential signal characteristics. Information obtained during receive detection may be analyzed to identify channel operational characteristics during normal operation and perform non-disruptive channel adjustments. Initialization or start-up adjustment may also be performed using intentionally transmitted patterns.

    摘要翻译： 矢量信令码通信系统依赖于使用多个信令信道的码元组的传输，这些信令信道必须被主动监视和调整以最小化差分信号特性。 可以分析在接收检测期间获得的信息，以在正常操作期间识别信道操作特性，并执行非中断信道调整。 初始化或启动调整也可以使用故意传输的模式进行。

    Multiply accumulate operations in the analog domain
    43.
    发明授权
    Multiply accumulate operations in the analog domain 有权
    在模拟域中乘以累加运算

    公开(公告)号：US09069995B1

    公开(公告)日：2015-06-30

    申请号：US13773066

    申请日：2013-02-21

    申请人： KANDOU LABS, S.A.

    发明人： Harm Cronie

    IPC分类号： G06G7/16

    CPC分类号： G06G7/16

    摘要： Fixed capacitive circuits are described which perform arithmetical summation operations over sets of scaled analog values, where the constant parameters of the summations and scaling multiplications are formed as ratios of circuit element values. The passive nature of the design can enable efficient integrated circuit implementation.

    摘要翻译： 描述了固定电容电路，其对缩放的模拟值集合执行算术求和操作，其中求和和缩放乘法的恒定参数形成为电路元件值的比率。 设计的被动性可以实现高效的集成电路实现。

    LOW POWER CHIP-TO-CHIP BIDIRECTIONAL COMMUNICATIONS
    45.
    发明申请
    LOW POWER CHIP-TO-CHIP BIDIRECTIONAL COMMUNICATIONS 有权

    公开(公告)号：US20230071030A1

    公开(公告)日：2023-03-09

    申请号：US18047610

    申请日：2022-10-18

    申请人： Kandou Labs, S.A.

    发明人： Ali Hormati

    IPC分类号： H04L25/02 ,  H04L25/49 ,  H04L25/08 ,  H04B3/14

    摘要： Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

    SYNCHRONOUSLY-SWITCHED MULTI-INPUT DEMODULATING COMPARATOR
    46.
    发明申请
    SYNCHRONOUSLY-SWITCHED MULTI-INPUT DEMODULATING COMPARATOR 有权

    公开(公告)号：US20230062846A1

    公开(公告)日：2023-03-02

    申请号：US18045713

    申请日：2022-10-11

    申请人： Kandou Labs, S.A.

    发明人： Armin Tajalli

    IPC分类号： H04L27/20 ,  H04L25/02 ,  H04L25/49 ,  H04L27/148 ,  H04L27/26

    摘要： Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.

    MULTI-WIRE PERMUTED FORWARD ERROR CORRECTION
    48.
    发明申请
    MULTI-WIRE PERMUTED FORWARD ERROR CORRECTION 有权

    公开(公告)号：US20220321255A1

    公开(公告)日：2022-10-06

    申请号：US17845638

    申请日：2022-06-21

    申请人： Kandou Labs, S.A.

    发明人： Amin Shokrollahi ,  Ali Hormati

    IPC分类号： H04L1/00 ,  H04L25/02 ,  H03M13/05 ,  H04J13/00 ,  H04L25/08 ,  H03M13/15 ,  H03M13/37 ,  H03M13/27 ,  H03M13/00

    摘要： Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.

    MULTILEVEL DRIVER FOR HIGH SPEED CHIP-TO-CHIP COMMUNICATIONS
    49.
    发明申请
    MULTILEVEL DRIVER FOR HIGH SPEED CHIP-TO-CHIP COMMUNICATIONS 有权

    公开(公告)号：US20220217024A1

    公开(公告)日：2022-07-07

    申请号：US17700182

    申请日：2022-03-21

    申请人： Kandou Labs, S.A.

    发明人： Roger Ulrich

    IPC分类号： H04L25/03 ,  H04B3/04 ,  H03K19/0185 ,  H03K19/00 ,  H04L25/49

    摘要： A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

    MULTI-MODAL DATA-DRIVEN CLOCK RECOVERY CIRCUIT
    50.
    发明申请
    MULTI-MODAL DATA-DRIVEN CLOCK RECOVERY CIRCUIT 有权

    公开(公告)号：US20220200606A1

    公开(公告)日：2022-06-23

    申请号：US17689649

    申请日：2022-03-08

    申请人： KANDOU LABS, S.A.

    发明人： Armin Tajalli ,  Ali Hormati

    IPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/099 ,  H03L7/23 ,  H03L7/08 ,  H03L7/093

    摘要： Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.