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公开(公告)号：US08564102B2
公开(公告)日：2013-10-22
申请号：US13108231
申请日：2011-05-16
Applicant: Ju-il Choi , Jae-hyun Phee , Kyu-ha Lee , Ho-jin Lee , Son-kwan Hwang
Inventor： Ju-il Choi , Jae-hyun Phee , Kyu-ha Lee , Ho-jin Lee , Son-kwan Hwang
CPC classification number: H01L21/76879 , H01L21/76844 , H01L21/76873 , H01L21/76898 , H01L24/05 , H01L24/06 , H01L2224/05009 , H01L2224/06181
Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.
Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括层间绝缘层图案，由形成在层间绝缘层图案中的通孔形成的通道暴露的金属线图案，以输入和输出电信号，以及直接接触金属线图案的镀层图案和 填充通孔。 该方法包括形成具有金属线图案的层间绝缘层，以输入和输出其中形成的电信号，形成通孔以限定延伸穿过层间绝缘层的通道，直到金属线图案的至少一部分露出 并且形成镀层图案以填充通孔并且通过使用通过通孔露出的金属线图案作为种子金属层直接接触金属线图案。
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42.发明申请
公开(公告)号：US20050280564A1
公开(公告)日：2005-12-22
申请号：US10951249
申请日：2004-09-27
Applicant: Kyu-Ha Lee
Inventor： Kyu-Ha Lee
CPC classification number: H03H17/0671
Abstract: Disclosed is a digital sampling rate converter for compensating for a drop of an in-band signal, the digital sampling rate converter including a CIC (Cascaded Integrator-Comb) decimator for performing a decimation operation at a first decimation ratio based on an overall decimation ratio, for an input signal; a sub-decimator for performing a decimation operation at a second decimation ratio for a signal output from the CIC decimator; and a compensation unit for performing at least two multiplication operations and two addition operations with respect to a signal output from the sub-decimator using a lowest operation clock frequency in an assigned band.
Abstract translation: 公开了一种数字采样率转换器，用于补偿带内信号的下降，该数字采样率转换器包括一个CIC（级联积分 - 梳状）抽取器，用于基于总抽取比率以第一抽取比率执行抽取运算 ，用于输入信号; 用于对从CIC抽取器输出的信号执行第二抽取比例的抽取操作的子抽取器; 以及补偿单元，用于使用分配频带中的最低操作时钟频率来执行关于从子抽取器输出的信号的至少两个乘法运算和两个相加运算。
