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公开(公告)号：US07583512B2
公开(公告)日：2009-09-01
申请号：US12023616
申请日：2008-01-31
Applicant: Chang Sup Ryu , Myung Sam Kang
Inventor： Chang Sup Ryu , Myung Sam Kang
IPC: H05K1/16
CPC classification number: H05K1/185 , H05K3/4069 , H05K3/4602 , H05K2201/09536 , H05K2201/10636 , H05K2203/063 , Y02P70/611 , Y10T29/49101 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
Abstract: Disclosed is a PCB including an embedded passive component and a method of fabricating the same. The PCB includes at least two circuit layers in which circuit patterns are formed. At least one insulating layer is interposed between the circuit layers. A pair of terminals is vertically formed through the insulating layers, plated with a first conductive material, and separated from each other by a predetermined distance. The embedded passive component is interposed between the terminals and has electrodes formed on both sides thereof. The electrodes are separated from the terminals by a predetermined distance and electrically connected to the terminals through a second conductive material.
Abstract translation: 公开了一种包括嵌入式无源元件的PCB及其制造方法。 PCB包括形成电路图案的至少两个电路层。 在电路层之间插入至少一个绝缘层。 一对端子通过绝缘层垂直地形成，镀有第一导电材料，并且彼此分开预定距离。 嵌入式无源部件插入在端子之间，并且具有形成在其两侧的电极。 电极与端子分开预定距离，并通过第二导电材料与端子电连接。
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公开(公告)号：US07550316B2
公开(公告)日：2009-06-23
申请号：US11715906
申请日：2007-03-09
Applicant: Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
Inventor： Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
CPC classification number: H01L23/3128 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/81801 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad. The board on chip package and the manufacturing method thereof according to the present invention can design a high density circuit since a circuit pattern is formed using a seed layer.
Abstract translation: 本发明的一个方面的特征在于片上封装的制造方法。 该方法可以包括：（a）在载体膜上层压干膜，其一面由薄金属膜层压; （b）通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; （c）去除干膜; （d）层压除了形成焊锡球焊盘的部分之外的上光阻焊剂; （e）蚀刻形成在上层光阻抗层未层叠的部分上的金属薄膜; （f）通过倒装芯片接合将半导体芯片安装在焊球垫上; （g）用钝化材料模制半导体芯片; （h）去除载体膜和金属薄膜; 和（i）在焊球垫下方层叠下光阻焊剂。 根据本发明的片上封装及其制造方法可以设计高密度电路，因为使用种子层形成电路图案。
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公开(公告)号：US20090095508A1
公开(公告)日：2009-04-16
申请号：US12149610
申请日：2008-05-05
Applicant: Jung-Hyun Park , Ji-Eun Kim , Myung-Sam Kang
Inventor： Jung-Hyun Park , Ji-Eun Kim , Myung-Sam Kang
CPC classification number: H05K3/205 , H01L21/4846 , H05K3/243 , H05K3/421 , H05K2201/09481 , H05K2203/0376 , H05K2203/0574 , Y10T29/49155
Abstract: A printed circuit board and a method for manufacturing the same are disclosed. The manufacturing method includes: forming a first plating resist corresponding to the circuit pattern on a surface of each of a first carrier and a second carrier; forming a second plating resist corresponding to the pad on each of the surfaces; forming the pad by performing plating over each of the surfaces; stripping the second plating resists; forming the circuit pattern by performing plating over each of the surfaces; pressing the first carrier and the second carrier with an insulation layer interposed between the first carrier and the second carrier such that the circuit patterns face each other; and removing the first carrier and the second carrier. Since plating bars need not be used, the degree of freedom in designing circuits can be increased, and circuits of higher densities can be designed.
Abstract translation: 公开了一种印刷电路板及其制造方法。 制造方法包括：在第一载体和第二载体的每一个的表面上形成与电路图案相对应的第一电镀抗蚀剂; 在每个表面上形成对应于所述垫的第二电镀抗蚀剂; 通过在每个表面上进行电镀来形成焊盘; 剥离第二电镀抗蚀剂; 通过在每个表面上进行电镀来形成电路图案; 用绝缘层将所述第一载体和所述第二载体按压在所述第一载体和所述第二载体之间，使得所述电路图案彼此面对; 以及去除所述第一载体和所述第二载体。 由于不需要使用电镀棒，因此能够提高设计电路的自由度，能够设计更高密度的电路。
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公开(公告)号：US20090011220A1
公开(公告)日：2009-01-08
申请号：US12153155
申请日：2008-05-14
Applicant: Jung-Hyun Park , Jeong-Woo Park , Sang-Duck Kim , Jong-Gyu Choi , Ji-Eun Kim , Myung-Sam Kang
Inventor： Jung-Hyun Park , Jeong-Woo Park , Sang-Duck Kim , Jong-Gyu Choi , Ji-Eun Kim , Myung-Sam Kang
CPC classification number: H05K3/205 , H05K3/108 , H05K3/4602 , H05K2203/1536 , Y10T428/249984 , Y10T428/31504 , Y10T428/31511 , Y10T428/3154 , Y10T428/31678 , Y10T428/31721 , Y10T428/31993
Abstract: A carrier and a method for manufacturing a printed circuit board are disclosed. The method for manufacturing a printed circuit board may include: forming a first circuit pattern on each of a pair of release layers, which are attached respectively to either side of a base layer by adhesive layers; detaching the pair of release layers from the base layer; stacking and pressing the pair of release layers onto either side of an insulation substrate such that the first circuit patterns are buried in the insulation substrate; and separating the pair of release layers. By forming a circuit pattern on each of a pair of release layers with a single process, and transferring the circuit pattern into each side of an insulation substrate, the manufacturing process can be shortened and circuit patterns can be formed to a high density.
Abstract translation: 公开了载体和制造印刷电路板的方法。 制造印刷电路板的方法可以包括：在一对剥离层中的每一个上形成第一电路图案，其分别通过粘合剂层附着在基层的任一侧; 将一对释放层从基层分离; 堆叠并将一对释放层压在绝缘基板的任一侧上，使得第一电路图案被埋在绝缘基板中; 并分离一对释放层。 通过利用单一工艺在一对释放层的每一个上形成电路图案，并将电路图案转移到绝缘基板的每一侧，可以缩短制造工艺并且可以以高密度形成电路图案。
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公开(公告)号：US20080315431A1
公开(公告)日：2008-12-25
申请号：US12155555
申请日：2008-06-05
Applicant: Jin-Yong Ahn , Chang-Sup Ryu , Byung-Youl Min , Myung-Sam Kang
Inventor： Jin-Yong Ahn , Chang-Sup Ryu , Byung-Youl Min , Myung-Sam Kang
CPC classification number: H05K1/113 , H01L23/13 , H01L23/49816 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H05K3/20 , H05K3/4644 , H05K2201/0376 , H05K2201/09472 , H01L2224/0401
Abstract: A mounting substrate and a method of manufacturing the mounting substrate. The mounting substrate can include an insulation layer, a bonding pad buried in one side of the insulation layer in correspondence with a mounting position of a chip, and a circuit pattern electrically connected to the bonding pad. By utilizing certain embodiments of the invention, the process for stacking a solder resist layer can be omitted, as the bonding pads can be implemented in a form recessed from the surface of the insulation layer. In this way, the manufacturing process can be simplified and manufacturing costs can be reduced. Since the surface of the mounting-substrate on which to mount a chip can be kept flat without any protuberances, the occurrence of voids in the underfill can be minimized. This is correlated to obtaining a high degree of reliability, and leads to a greater likelihood of successful mounting.
Abstract translation: 一种安装基板及其制造方法。 安装基板可以包括绝缘层，与绝缘层的一侧相对应于芯片的安装位置的接合焊盘以及电连接到焊盘的电路图案。 通过利用本发明的某些实施例，可以省略堆叠阻焊层的工艺，因为焊盘可以以从绝缘层的表面凹陷的形式来实施。 以这种方式，可以简化制造过程，并且可以降低制造成本。 由于安装芯片的安装基板的表面可以保持平坦而没有任何突起，所以可以使底部填充物中的空隙的发生最小化。 这与获得高可靠性相关，并且导致成功安装的可能性更大。
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公开(公告)号：US20080314633A1
公开(公告)日：2008-12-25
申请号：US12149522
申请日：2008-05-02
Applicant: Myung Sam Kang , Chin Kwan Kim
Inventor： Myung Sam Kang , Chin Kwan Kim
IPC: H01R12/04
CPC classification number: H05K3/4007 , H05K3/246 , H05K3/3457 , H05K3/4069 , H05K2201/0347 , H05K2201/0367 , H05K2201/0376 , H05K2201/09481 , H05K2201/09745
Abstract: A printed circuit board, which increases the contact area between an IC and a printed circuit board, thus increasing the degree of adhesion, is disclosed. The printed circuit board includes: an insulation layer which includes a first circuit pattern, including at least one via land, embedded in the upper surface of the insulation layer to be flush with the upper surface, and a second circuit pattern formed in the lower surface of the insulation layer to be flush with the lower surface; a solder resist layer formed on the insulation layer; a via hole and a bump integrally formed on the second circuit pattern through the via hole and the via land such that it protrudes from the insulation layer to be higher than the solder resist layer.
Abstract translation: 公开了一种印刷电路板，其增加了IC和印刷电路板之间的接触面积，从而增加了粘合度。 印刷电路板包括：绝缘层，其包括嵌入在绝缘层的上表面中以与上表面齐平的至少一个通孔焊盘的第一电路图案，以及形成在下表面中的第二电路图案 的绝缘层与下表面齐平; 形成在绝缘层上的阻焊层; 通孔和通过通孔和通孔焊盘一体地形成在第二电路图案上的突起，使得其从绝缘层突出成高于阻焊层。
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公开(公告)号：US20080101045A1
公开(公告)日：2008-05-01
申请号：US11976070
申请日：2007-10-19
Applicant: Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
Inventor： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
CPC classification number: H05K3/205 , H01L21/4846 , H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/15311 , H05K3/4007 , H05K2201/09745 , H05K2201/10674 , H05K2203/0338 , H05K2203/0435 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
Abstract: A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.
Abstract translation: 一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。 利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。
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公开(公告)号：US20080006942A1
公开(公告)日：2008-01-10
申请号：US11708568
申请日：2007-02-21
Applicant: Jung-Hyun Park , Byoung-Youl Min , Je-Gwang Yoo , Myung-Sam Kang , Hoe-Ku Jung , Ji-Eun Kim
Inventor： Jung-Hyun Park , Byoung-Youl Min , Je-Gwang Yoo , Myung-Sam Kang , Hoe-Ku Jung , Ji-Eun Kim
CPC classification number: H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06568 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A bottom substrate of package on package and manufacturing method thereof is disclosed. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.
Abstract translation: 公开了一种封装的底部衬底及其制造方法。 封装的封装的底部衬底通过焊球电连接到顶部衬底，所述焊球包括芯板，与所述焊球的位置对应地形成在所述芯板的表面上的焊球焊盘，绝缘体 层叠在芯板上的通孔，通过去除绝缘层的一部分使得焊球焊盘露出而形成的通孔以及填充在通孔中并与焊球电连接的金属层允许IC的数量 安装在底部基板上以增加焊球的尺寸，并且通过控制层叠在底部基板上的绝缘层的厚度，可以使焊球的尺寸和间距变小，由此更多的信号传输是 可能在顶部基板和底部基板之间。
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公开(公告)号：US20070281390A1
公开(公告)日：2007-12-06
申请号：US11727852
申请日：2007-03-28
Applicant: Myung-Sam Kang , Je-Gwang Yoo , Jung-Hyun Park , Ji-Eun Kim , Hoe-Ku Jung , Jin-Yong An
Inventor： Myung-Sam Kang , Je-Gwang Yoo , Jung-Hyun Park , Ji-Eun Kim , Hoe-Ku Jung , Jin-Yong An
IPC: H01L21/00
CPC classification number: H01L21/4846 , H01L23/49827 , H01L2924/0002 , H05K3/064 , H05K3/108 , H05K3/242 , H05K3/243 , H05K3/427 , H05K2201/0376 , H05K2203/0361 , H05K2203/1394 , H01L2924/00
Abstract: The present invention relates to a manufacturing method of a package substrate. A manufacturing method of a package substrate for mounting an electric component by connecting electrodes of the electric component to bonding pads, includes: manufacturing a buried pattern substrate having a circuit pattern and bonding pads buried in an insulating layer and having a seed layer laminated on the insulating layer, laminating a dry film onto the seed layer and removing the seed layer and the dry film of the upper side of the bonding pads, performing surface-treatment using the remaining seed layer as a plating lead; and removing the remaining seed layer and the dry film such that the circuit pattern is exposed.
Abstract translation: 本发明涉及封装基板的制造方法。 一种用于通过将电气部件的电极连接到接合焊盘来安装电气部件的封装基板的制造方法，包括：制造具有电路图案的掩埋图案基板和埋在绝缘层中并具有层叠在所述绝缘层上的种子层的接合焊盘 绝缘层，将干膜层压到种子层上，去除接合焊盘的上侧的种子层和干膜，使用剩余的种子层作为电镀引线进行表面处理; 并且除去剩余的种子层和干膜，使得电路图案被暴露。
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公开(公告)号：US20070210439A1
公开(公告)日：2007-09-13
申请号：US11715906
申请日：2007-03-09
Applicant: Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
Inventor： Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
CPC classification number: H01L23/3128 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/81801 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: An aspect of the present invention features a manufacturing method of a board on chip package. The method can comprise: (a) laminating a dry film on a carrier film, one side of which is laminated by a thin metal film; (b) patterning the dry film in accordance with a circuit wire through light exposure and developing process, and forming a solder ball pad and a circuit wire; (c) removing the dry film; (d) laminating an upper photo solder resist excluding a portion where the solder ball pad is formed; (e) etching the thin metal film formed on a portion where the upper photo solder resist is not laminated; (f) mounting a semiconductor chip on the solder ball pad by a flip chip bonding; (g) molding the semiconductor chip with a passivation material; (h) removing the carrier film and the thin metal film; and (i) laminating a lower photo solder resist under the solder ball pad. The board on chip package and the manufacturing method thereof according to the present invention can design a high density circuit since a circuit pattern is formed using a seed layer.
Abstract translation: 本发明的一个方面的特征在于片上封装的制造方法。 该方法可以包括：（a）在载体膜上层压干膜，其一面由薄金属膜层压; （b）通过曝光和显影工艺根据电路线图案化干膜，并形成焊球焊盘和电路线; （c）去除干膜; （d）层压除了形成焊锡球焊盘的部分之外的上光阻焊剂; （e）蚀刻形成在上层光阻抗层未层叠的部分上的金属薄膜; （f）通过倒装芯片接合将半导体芯片安装在焊球垫上; （g）用钝化材料模制半导体芯片; （h）去除载体膜和金属薄膜; 和（i）在焊球垫下方层叠下光阻焊剂。 根据本发明的片上封装及其制造方法可以设计高密度电路，因为使用种子层形成电路图案。
