公开(公告)号：US07772028B2

公开(公告)日：2010-08-10

申请号：US11959841

申请日：2007-12-19

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

IPC分类号： H01L21/66

CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

公开(公告)号：US07703060B2

公开(公告)日：2010-04-20

申请号：US11678069

申请日：2007-02-23

申请人： Timothy G. Dunham ,  Robert K. Leidy ,  Kevin N. Ogg ,  Richard J. Rassel ,  Valarmathi C. Shanmugam

发明人： Timothy G. Dunham ,  Robert K. Leidy ,  Kevin N. Ogg ,  Richard J. Rassel ,  Valarmathi C. Shanmugam

IPC分类号： G06F17/50

CPC分类号： G03F7/70475 ,  G03F7/70466 ,  G03F7/70691

摘要： Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout includes for at least one stitched region of a plurality of stitched regions: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithographic tool field at the second entity.

摘要翻译： 公布了拼接集成电路（IC）芯片布局方法，系统和程序产品。 在一个实施例中，一种方法包括从第一实体获得超过第二实体上的光刻工具区域的尺寸的IC芯片布局的电路设计，其中IC芯片布局包括用于多个 缝合区域：识别发生缝合的至少一个缝合区域的边界的边界标识和指示所述至少一个缝合区域是否是以下之一的类型指示器：冗余且唯一; 将IC芯片布局解剖为在第二实体处表示为唯一或冗余的缝合区域; 以及基于所述多个缝合区域在所述第二实体处产生光刻掩模版，所述光刻掩模版具有适合在所述第二实体处的所述光刻工具区域的尺寸内的尺寸。

公开(公告)号：US20100029021A1

公开(公告)日：2010-02-04

申请号：US12182668

申请日：2008-07-30

申请人： Brent A. Anderson ,  Robert K. Leidy ,  Jed H. Rankin

发明人： Brent A. Anderson ,  Robert K. Leidy ,  Jed H. Rankin

IPC分类号： H01L21/66

CPC分类号： G03F7/70866 ,  G03F7/7085 ,  G03F7/70975

摘要： Methods for real-time contamination, environmental, or physical monitoring of a photomask. An attribute of a photomask is monitored using a sensor of an electronics package attached to the photomask. The methods further include generating one or more sensor signals relating to the monitored attribute with the sensor and transmitting the one or more sensor signals from the electronics package to a control system.

摘要翻译： 光掩模的实时污染，环境或物理监测的方法。 使用附接到光掩模的电子封装的传感器监视光掩模的属性。 所述方法还包括利用所述传感器生成与所监视的属性相关的一个或多个传感器信号，并将所述一个或多个传感器信号从所述电子装置封装传送到控制系统。

公开(公告)号：US07655495B2

公开(公告)日：2010-02-02

申请号：US11623977

申请日：2007-01-17

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

公开(公告)号：US20090276739A1

公开(公告)日：2009-11-05

申请号：US12112336

申请日：2008-04-30

申请人： Robert K. Leidy ,  Kevin N. Ogg ,  Richard J. Rassel ,  Jeanne-Tania Sucharitaves

发明人： Robert K. Leidy ,  Kevin N. Ogg ,  Richard J. Rassel ,  Jeanne-Tania Sucharitaves

IPC分类号： G06F17/50

CPC分类号： G03F7/70475 ,  G03F1/00 ,  G03F1/50 ,  G03F7/70466

摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.

摘要翻译： 针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。 一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。 一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。

公开(公告)号：US07521798B2

公开(公告)日：2009-04-21

申请号：US11943277

申请日：2007-11-20

申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC分类号： H01L23/48

CPC分类号： H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20080315124A1

公开(公告)日：2008-12-25

申请号：US11767633

申请日：2007-06-25

申请人： Robert K. Leidy ,  Paul D. Sonntag ,  Peter J. Sullivan

发明人： Robert K. Leidy ,  Paul D. Sonntag ,  Peter J. Sullivan

IPC分类号： G21G5/00

CPC分类号： G03F7/70475 ,  G03F7/70466 ,  Y10S430/143

摘要： A method for manufacturing a stitched space in a semiconductor circuit implements a photolithographic process for printing one or more image fields on a wafer surface, each image field corresponding to a portion of a circuit or device and including a space that is to be stitched in adjacent image fields. The space to be stitched that is produced from an image field is overlapped onto the space to be stitched produced from the adjacent image field, however, the overlapped space from the adjacent image fields is intentionally misaligned. The stitched space is then subject to the double light exposure dose to print the stitched space, with the result that an overlay tolerance of the stitched space is improved.

摘要翻译： 用于制造半导体电路中的缝合空间的方法实现了用于在晶片表面上印刷一个或多个图像场的光刻工艺，每个图像场对应于电路或器件的一部分，并且包括将被相邻的缝合空间 图像字段。 从图像场产生的要缝制的空间被重叠在从相邻图像场产生的待缝合的空间上，然而，与相邻图像场的重叠空间被有意地对准。 然后缝合的空间经受双倍曝光剂量以打印缝合空间，结果是改善了缝合空间的覆盖公差。

公开(公告)号：US07176485B2

公开(公告)日：2007-02-13

申请号：US10920936

申请日：2004-08-18

申请人： Robert K. Leidy

发明人： Robert K. Leidy

IPC分类号： H01L23/532

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped region having a predetermined resistivity.

摘要翻译： 提供了一种用于确定在绝缘体中形成的镶嵌金属线的线宽的线宽测量结构。 所述线宽测量结构包括：形成在所述绝缘体中的镶嵌多晶硅线，所述多晶硅线具有具有预定电阻率的掺杂区域。

公开(公告)号：US06944578B2

公开(公告)日：2005-09-13

申请号：US10868411

申请日：2004-06-15

申请人： Reginald R. Bowley, Jr. ,  Vincent J. Carlos ,  James E. Doran ,  Stephen E. Knight ,  Robert K. Leidy ,  Keith J. Machia ,  Joseph E. Shaver ,  Dianne L. Sundling

发明人： Reginald R. Bowley, Jr. ,  Vincent J. Carlos ,  James E. Doran ,  Stephen E. Knight ,  Robert K. Leidy ,  Keith J. Machia ,  Joseph E. Shaver ,  Dianne L. Sundling

IPC分类号： G03F7/20 ,  G03F9/02 ,  G03C5/00

CPC分类号： G03F7/70625 ,  G03F7/70641

摘要： A method uses three dimensional feature metrology for implementation of critical image control and feedback of lithographic focus and x/y tilt. The method is for measuring 3 dimensional profile changes in a photo sensitive film and feeding back compensatory exposure tool focus corrections to maintain a stable lithographic process. The measured focus change from the optimal tool focus offset is monitored directly on the critical product images for both contact hole and line images. Z Focus corrections and x/y tilt corrections are fed back independently of dose to maintain critical dimension (CD) control. Additionally, the method can be used to diagnose problems with the focusing system by measuring the relationship between line edge width and barometric pressure.

摘要翻译： 一种方法使用三维特征计量来实现关键图像控制和光刻焦点和x / y倾斜的反馈。 该方法用于测量光敏膜中的三维轮廓变化，并反馈补偿曝光工具对焦校正以保持稳定的光刻过程。 从最佳工具对焦偏移测量的焦点变化直接监测接触孔和线图像的关键产品图像。 Z独立于剂量反馈对焦校正和x / y倾斜校正以维持关键尺寸（CD）控制。 此外，该方法可用于通过测量线边宽度和大气压力之间的关系来诊断聚焦系统的问题。

公开(公告)号：US06749969B2

公开(公告)日：2004-06-15

申请号：US09992767

申请日：2001-11-14

申请人： David V. Horak ,  Robert K. Leidy

发明人： David V. Horak ,  Robert K. Leidy

IPC分类号： G03F900

CPC分类号： G03F1/68 ,  G03F1/36

摘要： A reverse image mask is produced by initially depositing a metallic layer on a substrate. Resist is applied to the metallic layer to pattern desired features. The metallic layer is plated with a metal film, and the resist is then stripped. The metallic layer is etched using the metal film as a mask. Finally, the metal film is etched leaving the metallic layer etched in patterned areas to provide the reverse image mask.

摘要翻译： 通过最初在基底上沉积金属层来产生反向图像掩模。 将抗蚀剂施加到金属层以图案化所需特征。 金属层镀金属膜，然后剥离抗蚀剂。 使用金属膜作为掩模蚀刻金属层。 最后，蚀刻金属膜，留下在图案化区域中蚀刻的金属层，以提供反向图像掩模。