公开(公告)号：US06816825B1

公开(公告)日：2004-11-09

申请号：US09335755

申请日：1999-06-18

Applicant: Pranav Ashar ,  Srinivas Devadas ,  Farzan Fallah

Inventor： Pranav Ashar ,  Srinivas Devadas ,  Farzan Fallah

IPC: G06F1750

CPC classification number: G01R31/318307 ,  G01R31/318364

Abstract: A method of automatically generating vector sequences for an observability based coverage metric supports design validation. A design validation method for Register Transfer Level (RTL) circuits includes the generation of a tag list. Each tag in the tag list models an error at a location in HDL code at which a variable is assigned a value. Interacting linear and Boolean constraints are generated for the tag, and the set of constraints is solved using an HSAT solver to provide a vector that covers the tag. For each generated vector, tag simulation is performed to determine which others of the tags in the tag list are also covered by that vector. Vectors are generated until all tags have been covered, if possible within predetermined time constraints, thus automatically providing a set of vectors which will propagate errors in the HDL code to an observable output. Performance of the design validation method is enhanced through various heuristics involving path selection and tag magnitude maximization.

Abstract translation: 自动生成基于可观察性的覆盖度量向量序列的方法支持设计验证。 寄存器传输级（RTL）电路的设计验证方法包括生成标签列表。 标签列表中的每个标签在HDL代码中的变量分配了一个值的位置处模拟错误。 为标签生成交互线性和布尔约束，并使用HSAT求解器解决约束集，以提供覆盖标签的向量。 对于每个生成的矢量，执行标签模拟以确定标签列表中哪些标签中的哪些标签也被该向量覆盖。 如果可能的话在预定的时间限制内，直到所有标签被覆盖为止，才产生向量，从而自动地提供将HDL代码中的错误传播到可观察输出的一组向量。 通过涉及路径选择和标签幅度最大化的各种启发式方法，提高了设计验证方法的性能。