Directed self-assembly of block copolymers using segmented prepatterns
    41.
    发明授权
    Directed self-assembly of block copolymers using segmented prepatterns 有权
    使用分段预制图的嵌段共聚物的定向自组装

    公开(公告)号:US08398868B2

    公开(公告)日:2013-03-19

    申请号:US12468391

    申请日:2009-05-19

    摘要: An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls.

    摘要翻译: 例如使用光刻法形成衬底中的开口,其中开口具有侧壁,其横截面由轮廓和凸形的部分给出。 例如,开口的横截面可以由重叠的圆形区域给出。 侧壁在各个点处相邻,在那里它们限定突起。 将包含嵌段共聚物的聚合物层施加在开口和基底上,并允许自组装。 在开口中形成离散的,分离的畴,其被去除以形成孔,其可以转移到下面的基底中。 这些区域及其对应的孔的位置通过侧壁及其相关联的突起被引导到预定位置。 分离这些孔的距离可以大于或小于如果嵌段共聚物(和任何添加剂)在没有任何侧壁的情况下自组装就会发生。

    Integration process to improve focus leveling within a lot process variation
    42.
    发明授权
    Integration process to improve focus leveling within a lot process variation 有权
    整合过程可以在很多过程变化中提高焦点调平

    公开(公告)号:US08395228B2

    公开(公告)日:2013-03-12

    申请号:US12941375

    申请日:2010-11-08

    IPC分类号: H01L21/02

    摘要: A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.

    摘要翻译: 描述了改善半导体晶片的聚焦调平响应的方法。 该方法包括在半导体衬底上组合有机和无机或金属近红外(NIR)硬掩模; 在组合的有机NIR吸收和无机或金属NIR吸收硬掩模上形成抗反射涂层(ARC)层; 以及在所述ARC层上形成光致抗蚀剂层。 还描述了半导体结构,其包括基板,位于结构上方的抗蚀剂层; 以及位于衬底上方的吸收层。 吸收层包括无机或金属NIR吸收硬掩模层。

    Method for reducing side lobe printing using a barrier layer
    44.
    发明授权
    Method for reducing side lobe printing using a barrier layer 有权
    使用阻挡层减少旁瓣印刷的方法

    公开(公告)号:US08268542B2

    公开(公告)日:2012-09-18

    申请号:US11949190

    申请日:2007-12-03

    IPC分类号: G03F7/26

    CPC分类号: G03F7/095

    摘要: A method suitable for reducing side lobe printing in a photolithography process is enabled by the use of a barrier layer on top of a photoresist on a substrate. The barrier layer is absorbing at the imaging wavelength of the underlying photoresist and thus blocks the light from reaching the photoresist. A first exposure followed by a development in an aqueous base solution selectively removes a portion of the barrier layer to reveal a section of the underlying photoresist layer. At least a portion of the revealed section of the photoresist layer is then exposed and developed to form a patterned structure in the photoresist layer. The barrier layer can also be bleachable upon exposure and bake in the present invention.

    摘要翻译: 通过在基板上的光致抗蚀剂的顶部上使用阻挡层,能够实现在光刻工艺中减少旁瓣印刷的方法。 阻挡层在下面的光致抗蚀剂的成像波长处吸收,从而阻挡光到达光致抗蚀剂。 第一曝光随后在碱性水溶液中显影,选择性地除去阻挡层的一部分以露出下面的光致抗蚀剂层的一部分。 然后将光致抗蚀剂层的显露部分的至少一部分曝光和显影以在光致抗蚀剂层中形成图案化结构。 在本发明中曝光和烘烤时,阻挡层也可以是可漂白的。

    Method for removing threshold voltage adjusting layer with external acid diffusion process
    45.
    发明授权
    Method for removing threshold voltage adjusting layer with external acid diffusion process 有权
    用外部酸性扩散法去除阈值电压调节层的方法

    公开(公告)号:US08227307B2

    公开(公告)日:2012-07-24

    申请号:US12490353

    申请日:2009-06-24

    IPC分类号: H01L21/8238 H01L21/31

    摘要: The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.

    摘要翻译: 本发明提供一种形成阈值电压调节的栅极叠层的方法,其中使用外部酸扩散工艺来从半导体衬底的一个器件区域选择性地去除一部分阈值电压调节层。 外部酸扩散方法使用酸性聚合物,其在烘烤时表现出酸浓度的增加,其可以扩散到阈值电压调节层的下部暴露部分。 扩散的酸与阈值电压调节层的暴露部分反应,提供酸反应层,与不暴露于扩散的酸的阈值电压调节层的横向相邻部分相比,可以选择性地除去酸反应层。

    PHOTORESIST COMPOSITIONS AND METHODS FOR SHRINKING A PHOTORESIST CRITICAL DIMENSION
    47.
    发明申请
    PHOTORESIST COMPOSITIONS AND METHODS FOR SHRINKING A PHOTORESIST CRITICAL DIMENSION 失效
    光电复合材料组合物和方法,用于收缩光刻胶关键尺寸

    公开(公告)号:US20120070787A1

    公开(公告)日:2012-03-22

    申请号:US12883442

    申请日:2010-09-16

    IPC分类号: G03F7/20

    摘要: A method for reducing a photoresist critical dimension, the method comprising depositing a photoresist film on a substrate, wherein the photoresist film includes a thermal base generator; patterning the photoresist film to form a first patterned film possessing a first critical dimension; depositing a crosslinkable film over the first patterned film; heat-activating the first patterned film, either before or after depositing the crosslinkable film, to release a base in the first patterned film and cause crosslinking in the crosslinkable film in contact with the first patterned film; and developing the crosslinkable film to remove non-crosslinked soluble portions therein to form a second patterned film possessing a reduced critical dimension compared to the first critical dimension.

    摘要翻译: 一种降低光致抗蚀剂临界尺寸的方法,所述方法包括在基底上沉积光致抗蚀剂膜,其中光致抗蚀剂膜包括热碱发生器; 图案化光致抗蚀剂膜以形成具有第一临界尺寸的第一图案化膜; 在第一图案化膜上沉积可交联膜; 在沉积可交联膜之前或之后热激活第一图案化膜,以释放第一图案化膜中的碱,并引起与第一图案化膜接触的可交联膜的交联; 并且显影所述可交联膜以除去其中的非交联的可溶部分以形成与第一临界尺寸相比具有降低的临界尺寸的第二图案化膜。

    Gate Conductor Structure
    49.
    发明申请
    Gate Conductor Structure 有权
    门导体结构

    公开(公告)号:US20110156282A1

    公开(公告)日:2011-06-30

    申请号:US13010009

    申请日:2011-01-20

    IPC分类号: H01L29/423

    摘要: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.

    摘要翻译: 提供了具有在N型器件和P型器件之间的势垒区域的栅极导体结构,其中所述势垒区域最小化或消除了所述阻挡区域上的掺杂剂物质的交叉扩散。 阻挡区域包括栅极导体结构中的至少一个亚光刻间隙。 通过使用自组装共聚物在栅极导体结构上形成亚光刻图案掩模来形成亚光刻间隙。 根据一个实施例,至少一个亚光刻间隙是穿过栅极导体结构的宽度的狭缝或线。 亚光刻间隙足够深以使注入的掺杂剂从栅极导体的上部最小化或防止交叉扩散。 根据另一个实施例,亚光刻间隙具有足够的密度,使得在激活退火期间掺杂剂的交叉扩散减少或消除,使得Vt的变化最小化。

    Semiconductor structure and method of manufacturing same
    50.
    发明授权
    Semiconductor structure and method of manufacturing same 有权
    半导体结构及其制造方法

    公开(公告)号:US07960036B2

    公开(公告)日:2011-06-14

    申请号:US11831005

    申请日:2007-07-31

    IPC分类号: B32B9/00 B32B19/00 B32B15/04

    摘要: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

    摘要翻译: 半导体结构和半导体结构的制造方法,更具体地说,涉及具有降低的金属线电阻的半导体结构及其后端(BEOL)工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线,其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。