公开(公告)号：US06308304B1

公开(公告)日：2001-10-23

申请号：US09321785

申请日：1999-05-27

申请人： Anirudh Devgan ,  Peter Redmond O'Brien

发明人： Anirudh Devgan ,  Peter Redmond O'Brien

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： Realizable interconnect reduction techniques for on-chip RC interconnects are disclosed by first partitioning the original circuit into sets of two-port circuits to maintain the spatial sparsity of the reduced model. Each original two-port circuit is matched to a reduced RC circuit having a specific configuration. The moments of the original two-port circuits are calculated. Closed form expression values of the reduced circuit elements are then calculated from the moments of the original circuits. The closed form expressions for calculating the values of the elements in the reduced circuit use a reduced number of independent variables associated with the elements, thus simplifying the calculations. An efficient linear time moment computation technique is used for computing the moments for the two-port circuits.

摘要翻译： 公开了用于片上RC互连的可实现的互连减少技术，首先将原始电路划分为两端口电路组，以维持缩小模型的空间稀疏性。 每个原始双端口电路与具有特定配置的减小RC电路匹配。 计算原始双端口电路的时刻。 然后从原始电路的时刻计算电路元件的闭合表达式值。 用于计算简化电路中的元素的值的闭合形式表达式使用与元素相关联的减少数量的独立变量，从而简化了计算。 使用有效的线性时间矩计算技术来计算双端口电路的力矩。

公开(公告)号：US6117182A

公开(公告)日：2000-09-12

申请号：US94544

申请日：1998-06-12

申请人： Charles Jay Alpert ,  Stephen Thomas Quay ,  Anirudh Devgan

发明人： Charles Jay Alpert ,  Stephen Thomas Quay ,  Anirudh Devgan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068

摘要： A method for optimal insertion of buffers into an integrated circuit design. A model representative of a plurality of circuits is created where each circuit has a receiving node coupled to a conductor and a source. A receiving node is selected from the modeled plurality of circuits and circuit noise is calculated for the selected receiving node utilizing the circuit model. If the calculated circuit noise exceeds an acceptable value an optimum distance is computed from the receiving node on the conductor for buffer insertion. In a multi-sink circuit merging of the noise calculation for the two receiving circuits must be accomplished. If an intersection of conductors exists between the receiving node and the optimum distance a set of candidate buffer locations is generated. The method then prunes inferior solutions to provide an optimal insertion of buffers.

摘要翻译： 一种将缓冲器最佳插入集成电路设计的方法。 创建代表多个电路的模型，其中每个电路具有耦合到导体和源的接收节点。 从建模的多个电路中选择接收节点，并且利用电路模型为所选择的接收节点计算电路噪声。 如果计算出的电路噪声超过可接受的值，则从用于缓冲器插入的导体上的接收节点计算最佳距离。 在多宿电路中，必须实现两个接收电路的噪声计算合并。 如果在接收节点和最佳距离之间存在导体，则产生一组候选缓冲器位置。 该方法然后修剪较差的解决方案，以提供缓冲区的最佳插入。

公开(公告)号：US6029117A

公开(公告)日：2000-02-22

申请号：US963278

申请日：1997-11-03

申请人： Anirudh Devgan

发明人： Anirudh Devgan

IPC分类号： G01R31/00 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/002

摘要： An efficient method for identifying potential noise failures in an integrated circuit design by predicting peak noise within a victim circuit of an integrated circuit. Initially, a victim circuit within an integrated circuit is located. An aggressor circuit within the integrated circuit is located which has a physical relationship with the victim circuit, normally proximity. The slope of a signal within the aggressor circuit is analyzed and the coupling currents induced in the victim circuit by the aggressor circuit are computed. The input slope of the aggressor circuit and the physical relationship between the victim circuit and the aggressor circuit are utilized to determine a peak current induced into the victim circuit utilizing modelled coupling capacitance. The peak current and the equivalent impedance of the victim circuit can be utilized to determine peak noise. Noise failures on integrated circuits can be avoided by detecting peak noise which is above acceptable levels.

摘要翻译： 通过预测集成电路的受害电路内的峰值噪声来识别集成电路设计中的潜在噪声故障的有效方法。 最初，位于集成电路内的受害电路。 位于集成电路内的侵略电路，其与受害电路具有物理关系，通常为接近。 分析侵略者电路内的信号的斜率，并计算由侵略者电路在受害电路中感应的耦合电流。 利用侵略电路的输入斜率和受害电路与侵略电路之间的物理关系，利用建模的耦合电容来确定感应到受害电路的峰值电流。 可以利用受害电路的峰值电流和等效阻抗来确定峰值噪声。 通过检测高于可接受水平的峰值噪声可以避免集成电路的噪声故障。