公开(公告)号：US20130222162A1

公开(公告)日：2013-08-29

申请号：US13408173

申请日：2012-02-29

申请人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

发明人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

IPC分类号： H03M1/10 ,  H03M1/66

CPC分类号： H03M1/1047 ,  H03M1/745 ,  H03M1/785

摘要： An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

摘要翻译： 使用主数模转换器（DAC）和子DAC将输入数字信号转换为模拟信号。 从输入数字信号中减去偏移值，以生成偏移调整数字信号。 主DAC将偏移调整后的数字信号转换为第一个模拟信号。 基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。 子DAC将第二数字转换为第二模拟信号，当与第一模拟信号组合时，其提供输入数字信号的模拟表示。

公开(公告)号：US08471629B2

公开(公告)日：2013-06-25

申请号：US13173791

申请日：2011-06-30

申请人： Axel Thomsen ,  Zhongda Wang ,  Sai Chu Wong ,  Yunteng Huang

发明人： Axel Thomsen ,  Zhongda Wang ,  Sai Chu Wong ,  Yunteng Huang

IPC分类号： H03F1/14 ,  H03G3/20

CPC分类号： H03G3/34 ,  H03G3/3042

摘要： A power control circuit is coupled to receive a feedback signal from a power amplifier (PA) and generate a control signal to control a variable gain amplifier (VGA) coupled to an input to the PA based on the feedback signal. The power control circuit may include, in one embodiment, a mute circuit to generate a mute signal to be provided to the VGA when the control signal is less than a first level and a clamp circuit to clamp a control voltage used to generate the control signal from exceeding a threshold level.

摘要翻译： 功率控制电路被耦合以从功率放大器（PA）接收反馈信号，并产生控制信号，以根据反馈信号控制耦合到PA的输入的可变增益放大器（VGA）。 在一个实施例中，功率控制电路可以包括静音电路，以在控制信号小于第一电平时产生要提供给VGA的静音信号，以及钳位电路来钳位用于产生控制信号的控制电压 超过阈值水平。

公开(公告)号：US20110050198A1

公开(公告)日：2011-03-03

申请号：US12551788

申请日：2009-09-01

申请人： Zhiwei Dong ,  William W. K. Tang ,  Axel Thomsen

发明人： Zhiwei Dong ,  William W. K. Tang ,  Axel Thomsen

IPC分类号： G05F3/16

CPC分类号： G05F3/242 ,  G05F1/607

摘要： A technique for reducing power dissipation and circuit area for a high voltage application includes creating a low-voltage, local power supply for use with local circuitry. In at least one embodiment of the invention, an apparatus includes an output node configured to provide a regulated output voltage. The apparatus includes a variable current source coupled to a first power supply node, wherein the variable current source is configured to provide an output current to the output node based on a control signal on a control node. The apparatus includes a feedback circuit configured to generate the control signal based on a mirrored current. The mirrored current is a mirrored version of a residual current flowing between the output node and a second power supply node. The regulated output voltage has a voltage level less than the voltage level on the first power supply node.

摘要翻译： 用于降低功率耗散和高电压应用的电路面积的技术包括产生用于本地电路的低电压本地电源。 在本发明的至少一个实施例中，一种装置包括被配置成提供调节输出电压的输出节点。 该装置包括耦合到第一电源节点的可变电流源，其中可变电流源被配置为基于控制节点上的控制信号向输出节点提供输出电流。 该装置包括被配置为基于镜像电流产生控制信号的反馈电路。 镜像电流是在输出节点和第二电源节点之间流动的剩余电流的镜像版本。 调节输出电压具有小于第一电源节点上的电压电平的电压电平。

公开(公告)号：US20080211588A1

公开(公告)日：2008-09-04

申请号：US11571077

申请日：2005-06-28

申请人： Douglas R. Frey ,  Axel Thomsen ,  Ligang Zhang

发明人： Douglas R. Frey ,  Axel Thomsen ,  Ligang Zhang

IPC分类号： H03L7/00 ,  H03B5/30

CPC分类号： H03L7/0891 ,  H03L7/1976

摘要： A noise cancellation signal is generated for a fractional-N phase-locked loop (200). A divide value is provided to a first delta sigma modulator circuit (203), which generates a divide control signal to control a divide value of a feedback divider (208) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator (320) to generate an integrated error term (x), where xk+1=xk+ek; and a phase error correction circuit (209) utilizes the error term ek and the integrated error term xk to generate the phase error cancellation signal.

摘要翻译： 对于分数N锁相环（200）产生噪声消除信号。 分频值被提供给第一ΔΣ调制器电路（203），其产生除法控制信号以控制锁相环中的反馈分频器（208）的除法值。 生成指示所生成的除法控制信号和提供给第一ΔΣ调制器电路的除法值之间的差异的误差项（e）。 误差项被集成在积分器（320）中，以产生积分误差项（x），其中x k + 1 + x + / SUP>; 并且相位误差校正电路（209）利用误差项e≠k和积分误差项x≠k来产生相位误差消除信号。

公开(公告)号：US07342460B2

公开(公告)日：2008-03-11

申请号：US11278326

申请日：2006-03-31

申请人： Jeffrey S. Batchelor ,  Axel Thomsen

发明人： Jeffrey S. Batchelor ,  Axel Thomsen

IPC分类号： H03L7/18

CPC分类号： H03L7/1976 ,  H03L1/026 ,  H03L1/027 ,  H03L7/0992 ,  H03L7/10 ,  H03L7/197 ,  H03L7/23

摘要： A technique provides a clock source that meets accuracy requirements, allows the use of a low cost resonator, provides a wide range of output frequencies, and provides suitable phase noise performance. The technique generates a clock signal having a target output frequency using a controllable oscillator having at least one continuous frequency range of operation. The technique dynamically adjusts a reference control value based on a voltage for adjusting a frequency of the clock signal around a frequency determined by the reference control value. The reference control value is adjusted to be approximately within the center of an actual pull range corresponding to the controllable oscillator and a voltage control input of the controllable oscillator. The effective pull range of the controllable oscillator is continuous across the at least one continuous frequency range of operation.

摘要翻译： 一种技术提供了满足精度要求的时钟源，允许使用低成本谐振器，提供宽范围的输出频率，并提供合适的相位噪声性能。 该技术使用具有至少一个连续的操作频率范围的可控振荡器来产生具有目标输出频率的时钟信号。 该技术基于用于调整围绕由参考控制值确定的频率的时钟信号的频率的电压来动态地调整参考控制值。 参考控制值被调整为大约在对应于可控振荡器的实际牵引范围的中心和可控振荡器的电压控制输入的中心。 可控振荡器的有效牵引范围在至少一个连续的操作频率范围内是连续的。

公开(公告)号：US07288998B2

公开(公告)日：2007-10-30

申请号：US11270957

申请日：2005-11-10

申请人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein ,  Derrick C. Wei

发明人： Axel Thomsen ,  Yunteng Huang ,  Jerrell P. Hein ,  Derrick C. Wei

IPC分类号： H03L7/00

CPC分类号： H03L7/0898 ,  H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/197 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03L2207/50 ,  H04J3/0688

摘要： A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.

摘要翻译： 电压控制时钟合成器包括接收定时参考信号的锁相环（PLL）电路，提供振荡器输出信号的可控振荡器电路，例如VCO，以及耦合到振荡器输出信号的反馈分频器电路。 振荡器输出信号的频率部分地根据用于产生确定反馈分频器电路的分频比的第一数字控制信号的存储值来确定。 存在于电压控制输入端的控制电压根据由存储的值确定的频率调整振荡器输出信号的频率。 控制电压被转换为第二数字信号，并用于与所存储的值组合确定第一数字控制信号。

公开(公告)号：US20070146083A1

公开(公告)日：2007-06-28

申请号：US11681941

申请日：2007-03-05

申请人： Jerrell Hein ,  Axel Thomsen

发明人： Jerrell Hein ,  Axel Thomsen

IPC分类号： H03L7/00

CPC分类号： H03L1/022 ,  H03L1/026 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/1976 ,  H03L7/235 ,  H03L2207/50

摘要： A clock device having a resonating device such as a crystal of SAW supplying a controllable oscillator such as a digitally controlled oscillator is calibrated by supplying a calibration clock. A phase-locked loop is utilized to generate one or more correction factors causing the PLL to lock to the calibration clock. The one or more correction factors are then stored in non-volatile memory.

摘要翻译： 通过提供校准时钟来校准具有诸如数字控制振荡器等可控振荡器的SAW的晶体谐振装置的时钟装置。 利用锁相环产生一个或多个校正因子，使PLL锁定到校准时钟。 然后将一个或多个校正因子存储在非易失性存储器中。

公开(公告)号：US07187216B2

公开(公告)日：2007-03-06

申请号：US10878198

申请日：2004-06-28

申请人： Lizhong Sun ,  Douglas F. Pastorello ,  Richard J. Juhn ,  Axel Thomsen

发明人： Lizhong Sun ,  Douglas F. Pastorello ,  Richard J. Juhn ,  Axel Thomsen

IPC分类号： H03K21/00

CPC分类号： H03K23/66 ,  H03L7/193 ,  H03L7/1976

摘要： A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.

摘要翻译： 相位选择分频电路包括接收具有共同频率和不同相位的多个信号的选择电路。 选择具有第一相位的多个信号中的一个作为选择器电路输出信号。 对应于第一相位的第一值与对应于从第一相位的相位偏移的第二值相加，以产生指示其的和。 该和用于选择具有第二相位的第二信号作为下一个选择器电路输出信号。 当产生连续的和时，由选择器电路提供具有期望频率的脉冲串。

公开(公告)号：US07113009B2

公开(公告)日：2006-09-26

申请号：US10807852

申请日：2004-03-24

申请人： Lizhong Sun ,  Bruce Del Signore ,  Axel Thomsen ,  Douglas F. Pastorello

发明人： Lizhong Sun ,  Bruce Del Signore ,  Axel Thomsen ,  Douglas F. Pastorello

IPC分类号： H03K25/00

CPC分类号： H03K21/40 ,  H03K21/08 ,  H03K23/667

摘要： A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.

摘要翻译： 本文公开了一种分频器。 分频器包括可编程地耦合以提供各种分频比的分频级序列。 分频器还包括一个或多个多路复用器，用于将分频级的输出反馈到除法级序列之前的分频级的输入端。 分频器还可以包括占空比校正电路和用于校正异常逻辑状态的自校正逻辑。 分级阶段可以相互同步运行。 多路复用器功能，自校正电路功能和分频功能可以在组合锁存电路中实现。

公开(公告)号：US08681026B2

公开(公告)日：2014-03-25

申请号：US13408173

申请日：2012-02-29

申请人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

发明人： Jinwen Xiao ,  Pavel Konecny ,  Axel Thomsen ,  Ka Y. Leung

IPC分类号： H03M1/06

CPC分类号： H03M1/1047 ,  H03M1/745 ,  H03M1/785

摘要： An input digital signal is converted to an analog signal using a main digital to analog converter (DAC) and a sub DAC. An offset value is subtracted from the input digital signal to generate an offset adjusted digital signal. The main DAC converts the offset adjusted digital signal to a first analog signal. A second digital signal is generated based on the offset value and a correction factor determined, at least in part, during calibration of the main DAC. The sub DAC converts the second digital to a second analog signal, which when combined with the first analog signal, provides an analog representation of the input digital signal.

摘要翻译： 使用主数模转换器（DAC）和子DAC将输入数字信号转换为模拟信号。 从输入数字信号中减去偏移值，以生成偏移调整数字信号。 主DAC将偏移调整后的数字信号转换为第一个模拟信号。 基于偏移值和至少部分地在主DAC的校准期间确定的校正因子来生成第二数字信号。 子DAC将第二数字转换为第二模拟信号，当与第一模拟信号组合时，该模拟信号提供输入数字信号的模拟表示。