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    Adaptive low latency receive queues
    46.
    发明授权
    Adaptive low latency receive queues 失效
    自适应低延迟接收队列

    公开(公告)号：US08265092B2

    公开(公告)日：2012-09-11

    申请号：US11855401

    申请日：2007-09-14

    申请人： David Craddock ,  Thomas A. Gregg ,  Thomas Schlipf

    发明人： David Craddock ,  Thomas A. Gregg ,  Thomas Schlipf

    IPC分类号： H04L12/28

    CPC分类号： G06F13/4022

    摘要： A receive queue provided in a computer system holds work completion information and message data together. An InfiniBand hardware adapter sends a single CQE+message data to the computer system that includes the completion Information and data. This information is sufficient for the computer system to receive and process the data message, thereby providing a highly scalable low latency receiving mechanism.

    摘要翻译： 计算机系统中提供的接收队列将工作完成信息和消息数据保存在一起。 InfiniBand硬件适配器将单个CQE +消息数据发送到包括完成信息和数据的计算机系统。 该信息足以使计算机系统接收和处理数据消息，从而提供高度可扩展的低延迟接收机制。

    Delaying acknowledgment of an operation until operation completion confirmed by local adapter read operation
    49.
    发明授权
    Delaying acknowledgment of an operation until operation completion confirmed by local adapter read operation 有权
    延迟确认操作，直到操作完成通过本地适配器读取操作确认

    公开(公告)号：US08589603B2

    公开(公告)日：2013-11-19

    申请号：US12871532

    申请日：2010-08-30

    申请人： David Craddock ,  Thomas A. Gregg

    发明人： David Craddock ,  Thomas A. Gregg

    IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/00 ,  G06F13/42

    CPC分类号： G06F13/28

    摘要： A request to perform an operation, such as a remote direct memory access (RDMA) write operation or a send operation that writes to memory, is sent from a sending input/output (I/O) adapter (e.g., an RDMA-capable adapter) to a receiving I/O adapter. The receiving I/O adapter receives the request and initiates performance of the operation, but delays sending an acknowledgment for the operation. The acknowledgment is delayed until the operation is complete (i.e., until the memory is updated and the data is visible to the remote processor), as determined by a read operation initiated and performed by the receiving I/O adapter transparent to the sending I/O adapter.

    摘要翻译： 从发送输入/输出（I / O）适配器（例如，支持RDMA的适配器）发送执行诸如远程直接存储器访问（RDMA）写入操作或写入存储器的发送操作之类的操作的请求 ）到接收I / O适配器。 接收I / O适配器接收请求并发起操作的性能，但延迟发送操作的确认。 确认被延迟，直到操作完成（即，直到存储器被更新并且数据对于远程处理器可见），由接收I / O适配器发起和执行的读操作确定，该读操作对发送I / O适配器。

    Associating input/output device requests with memory associated with a logical partition
    50.
    发明授权
    Associating input/output device requests with memory associated with a logical partition 有权
    将输入/输出设备请求与与逻辑分区关联的内存相关联

    公开(公告)号：US08417911B2

    公开(公告)日：2013-04-09

    申请号：US12821224

    申请日：2010-06-23

    申请人： David Craddock ,  Thomas A. Gregg ,  Eric N. Lais

    发明人： David Craddock ,  Thomas A. Gregg ,  Eric N. Lais

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00

    CPC分类号： G06F13/16 ,  G06F2213/0026

    摘要： An address controller includes a bit selector that receives a first portion of a requester id and selects a bit from a vector that identifies whether a requesting function is an SR-IOV device or a standard PCIe device. The controller also includes a selector coupled to the bit selector that forms an output comprised of either a second portion of the RID or a first portion of the address portion based on an input received from the selector and an address control unit that receives the first portion of the RID and the output and determines the LPAR that owns the requesting function based thereon, the address control unit providing the corrected memory request to the memory.

    摘要翻译： 地址控制器包括位选择器，其接收请求者id的第一部分，并从标识请求功能是SR-IOV设备还是标准PCIe设备的向量中选择一个位。 控制器还包括耦合到比特选择器的选择器，其基于从选择器接收的输入形成由RID的第二部分或地址部分的第一部分组成的输出，以及接收第一部分的地址控制单元 的RID和输出，并且基于此来确定拥有请求功能的LPAR，地址控制单元向存储器提供校正的存储器请求。