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86 条记录 (耗时 0.028 秒)

    Current cancellation for non-volatile memory
    41.
    发明授权
    Current cancellation for non-volatile memory 有权
    当前取消非易失性存储器

    公开(公告)号：US07965565B2

    公开(公告)日：2011-06-21

    申请号：US12502208

    申请日：2009-07-13

    申请人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

    发明人： Chulmin Jung ,  Insik Jin ,  YoungPil Kim ,  Yong Lu ,  Harry Hongyue Liu ,  Andrew John Carter

    IPC分类号： G11C7/00

    CPC分类号： G11C11/1673

    摘要： A method and apparatus for reading data from a non-volatile memory cell. In some embodiments, a cross-point array of non-volatile memory cells is arranged into rows and columns that are each controlled by a line driver. A read circuit is provided that is capable of reading a logical state of a predetermined memory cell by differentiating a non-integrated first reference value from a non-integrated second reference value. Further, each reference value is measured immediately after configuring the column corresponding to the predetermined memory cell to produce a first and second amount of current.

    摘要翻译： 一种用于从非易失性存储单元读取数据的方法和装置。 在一些实施例中，非易失性存储器单元的交叉点阵列被布置成行和列，每个行和列都由线驱动器控制。 提供读取电路，其能够通过将非积分的第一参考值与非积分的第二参考值进行微分来读取预定存储器单元的逻辑状态。 此外，在配置与预定存储单元相对应的列之后立即测量每个参考值以产生第一和第二电流量。

    NAND flash memory with integrated bit line capacitance
    43.
    发明授权
    NAND flash memory with integrated bit line capacitance 有权
    具有集成位线电容的NAND闪存

    公开(公告)号：US08050092B2

    公开(公告)日：2011-11-01

    申请号：US12474463

    申请日：2009-05-29

    申请人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

    发明人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

    IPC分类号： G11C11/34 ,  G11C11/24

    CPC分类号： G11C11/005 ,  G11C16/26 ,  G11C2216/14

    摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of the cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.

    摘要翻译： 用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。 根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。 在一些实施例中，易失性存储器单元是来自单元行的动态随机存取存储器（DRAM）单元，每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元 包括以NAND配置连接的闪存单元。

    Floating Source Line Architecture for Non-Volatile Memory
    44.
    发明申请
    Floating Source Line Architecture for Non-Volatile Memory 有权
    非易失性存储器的浮动源线架构

    公开(公告)号：US20100124095A1

    公开(公告)日：2010-05-20

    申请号：US12272507

    申请日：2008-11-17

    申请人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

    发明人： Chulmin Jung ,  Yong Lu ,  Harry Hongyue Liu

    IPC分类号： G11C11/00 ,  G11C11/416 ,  G11C8/08 ,  G11C11/02

    CPC分类号： G11C13/0002 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0069

    摘要： A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.

    摘要翻译： 一种用于将数据写入诸如RRAM存储器单元的非易失性存储单元的方法和装置。 在一些实施例中，非易失性存储单元的半导体阵列包括电阻感测元件（RSE）和开关器件。 多个存储单元的RSE连接到位线，而多个存储单元的开关器件连接到字线并被操作以选择存储器单元。 源极线连接到开关器件，并将一系列存储器单元连接在一起。 此外，驱动器电路连接到位线，并且通过使写入电流沿着通过所选择的RSE的写入电流路径并且通过至少一部分所述选择的RSE而将所选择的源极线的选定RSE写入所选择的电阻状态 剩余的RSE连接到所选择的源线。

    Semiconductor Control Line Address Decoding Circuit
    47.
    发明申请
    Semiconductor Control Line Address Decoding Circuit 有权
    半导体控制线地址解码电路

    公开(公告)号：US20110007597A1

    公开(公告)日：2011-01-13

    申请号：US12502219

    申请日：2009-07-13

    申请人： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

    发明人： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

    IPC分类号： G11C8/10

    CPC分类号： G11C8/10

    摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.

    摘要翻译： 用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。 根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。 耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压 并且向剩余的2N-1个输出线同时施加第二电压。

    ARRAY SENSE AMPLIFIERS, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF OPERATION
    48.
    发明申请
    ARRAY SENSE AMPLIFIERS, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF OPERATION 有权
    阵列感知放大器，包括其的存储器件和系统以及操作方法

    公开(公告)号：US20100019804A1

    公开(公告)日：2010-01-28

    申请号：US12573750

    申请日：2009-10-05

    申请人： Chulmin Jung ,  Tae Kim

    发明人： Chulmin Jung ,  Tae Kim

    IPC分类号： H03F3/45

    CPC分类号： G11C7/065 ,  G11C11/4091

    摘要： A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.

    摘要翻译： 描述了具有减小的增益的放大器级的读出放大器。 读出放大器包括第一输入/输出（“I / O”）节点和第二互补I / O节点。 读出放大器包括两个放大器级，每个用于放大I / O节点之一上的信号。 具有第一导电类型的第一放大器级将第一电压的I / O节点之一放大。 具有第二导电类型的第二放大器级将第二电压放大到另一个I / O节点。 读出放大器还包括耦合到第二放大器级的电阻电路，以减小第二放大器级的增益，从而降低相应I / O节点上的信号的放大率。

    Power saving sensing scheme for solid state memory
    50.
    发明授权
    Power saving sensing scheme for solid state memory 有权
    固态存储器的省电感测方案

    公开(公告)号：US07567465B2

    公开(公告)日：2009-07-28

    申请号：US11847559

    申请日：2007-08-30

    申请人： Chulmin Jung ,  Kang Yong Kim

    发明人： Chulmin Jung ,  Kang Yong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C8/12 ,  G11C7/103 ,  G11C8/18

    摘要： Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a memory array. States of a plurality of data bits stored in the selected plurality of memory cells are determined. In determining the states of the plurality of data bits, a portion of the plurality of data bits are sensed faster than others. The plurality of data bits are sequentially provided as an output. In one embodiment, the portion of the plurality of data bits includes the first bit of the sequential output of the memory device.

    摘要翻译： 公开了诸如涉及固态存储器件的方法和装置。 一种这样的方法包括选择存储器阵列中的多个存储器单元。 确定存储在所选择的多个存储单元中的多个数据位的状态。 在确定多个数据位的状态时，多个数据位的一部分被感测得比其他数据位更快。 顺序提供多个数据位作为输出。 在一个实施例中，多个数据位的部分包括存储器件的顺序输出的第一位。