摘要:
A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要:
A semiconductor structure includes raised source and drain regions, where the raised source and drain regions are facet free and unconstrained to have a shape conforming to a same crystallographic axes with respect to each other.
摘要:
A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.
摘要:
A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.
摘要:
The present disclosure relates to an improved method of providing a Ni silicide metal contact on a silicon surface by electrodepositing a Ni film on a silicon substrate. The improved method results in a controllable silicide formation wherein the silicide has a uniform thickness. The metal contacts may be incorporated in, for example, CMOS devices, MEM (micro-electro-mechanical) devices, and photovoltaic cells.
摘要:
A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.
摘要:
A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si2 alloy, and selectively etching the unreacted Si.
摘要:
A method of reducing contact resistance of metal silicides to a silicon-containing substrate is provided. The method includes first forming a metal germanium layer over a silicon-containing substrate. An optionally oxygen barrier layer may be formed over the metal germanium layer. Next, the structure containing the metal germanium layer is annealed at a temperature effective in converting at least a portion of the metal germanium layer into a substantially non-etchable metal silicide layer, while forming a Si-Ge interlayer between the substrate and the silicide layer. After annealing, the optional oxygen barrier layer and any remaining metal germanium layer is removed from the substrate.
摘要:
A method of substantially reducing Si consumption and bridging during metal silicide contact formation comprising the steps of: (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to said metal silicon alloy or pure metal; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase. An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).
摘要:
A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide portion, a nanostructure formed over the insulating and carbon portion and connecting the metal carbide source portion to the metal carbide drain portion, and a gate stack formed on over at least a portion of the insulating carbon portion and at least a portion of the nanostructure.