公开(公告)号：US20130156336A1

公开(公告)日：2013-06-20

申请号：US13585726

申请日：2012-08-14

申请人： Jung Hee Suk ,  Sanghun Yoon ,  Chun-Gi Lyuh ,  Ik Jae Chun ,  Tae Moon Roh

发明人： Jung Hee Suk ,  Sanghun Yoon ,  Chun-Gi Lyuh ,  Ik Jae Chun ,  Tae Moon Roh

IPC分类号： G06K9/36 ,  G06K9/40

CPC分类号： G06T3/0068

摘要： Disclosed is an image registration device which includes an image input unit which receives an image; an image information generating unit which generates a homography matrix from the input image; and a warping unit which registers an image based on the homography matrix. The registration information generating unit comprises a distance information generator which generates distance information on subjects of the input image; a distance information modeler which approximates the generated distance information; an overlap information generator which generates overlap information from the approximated distance information; a matching pair determiner which determines a matching pair from the overlap information; and a homography matrix generator which generates a homography matrix from the matching pair.

摘要翻译： 公开了一种图像注册装置，其包括接收图像的图像输入单元; 图像信息生成单元，其从输入图像生成单应性矩阵; 以及基于单应性矩阵来登记图像的翘曲单元。 所述登记信息生成部包括距离信息生成部，其生成与所述输入图像对象相对应的距离信息; 距离信息建模器近似所生成的距离信息; 重叠信息生成器，其从所述近似距离信息生成重叠信息; 匹配对确定器，其从所述重叠信息确定匹配对; 以及从匹配对生成单应性矩阵的单应性矩阵生成器。

公开(公告)号：US20120314940A1

公开(公告)日：2012-12-13

申请号：US13475867

申请日：2012-05-18

申请人： Sanghun YOON ,  Chun-Gi Lyuh ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh

发明人： Sanghun YOON ,  Chun-Gi Lyuh ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh

IPC分类号： G06K9/62

CPC分类号： G06K9/6239 ,  G06K9/6269

摘要： An image recognition device in accordance with the inventive concept may include an input vector extraction part extracting an input vector from an input image; a compression vector conversion part converting the input vector into a compression vector using a projection vector; a training parameter generation part receiving a training vector to generate a training parameter using a projection vector obtained through a folding operation of the training vector; and an image classification part classifying the compression vector using the training vector to output image recognition data.

摘要翻译： 根据本发明构思的图像识别装置可以包括从输入图像提取输入向量的输入向量提取部分; 压缩矢量转换部分，使用投影矢量将输入矢量转换为压缩矢量; 训练参数生成部，使用通过训练矢量的折叠操作得到的投影矢量，接收训练矢量，生成训练参数; 以及图像分类部分，使用训练矢量对压缩矢量进行分类，以输出图像识别数据。

公开(公告)号：US20120095947A1

公开(公告)日：2012-04-19

申请号：US13189345

申请日：2011-07-22

申请人： Sanghun Yoon ,  Chun-Gi Lyuh ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh

发明人： Sanghun Yoon ,  Chun-Gi Lyuh ,  Ik Jae Chun ,  Jung Hee Suk ,  Tae Moon Roh

IPC分类号： G06N5/02

CPC分类号： G06N20/00

摘要： Provided is a vector classifier and a vector classification method. The vector classifier includes a vector compressor configured to compress an input vector; a support vector storage unit configured to store a compressed support vector; and a support vector machine operation unit configured to receive the compressed input vector and the compressed support vector and perform an arithmetic operation according to a classification determining equation.

摘要翻译： 提供了一种向量分类器和向量分类方法。 矢量分类器包括被配置为压缩输入矢量的矢量压缩器; 配置为存储压缩的支持向量的支持向量存储单元; 以及支持向量机操作单元，被配置为接收压缩输入向量和压缩支持向量，并根据分类确定方程执行算术运算。

公开(公告)号：US20120092489A1

公开(公告)日：2012-04-19

申请号：US13012246

申请日：2011-01-24

申请人： Chun-Gi LYUH ,  Ik Jae Chun ,  Jung Hee Suk ,  Sanghun Yoon ,  Tae Moon Roh

发明人： Chun-Gi LYUH ,  Ik Jae Chun ,  Jung Hee Suk ,  Sanghun Yoon ,  Tae Moon Roh

IPC分类号： H04N7/18 ,  G06K9/46

CPC分类号： H04N7/183 ,  G06K9/6203

摘要： Provided is an image recognizing method. The image recognizing method includes selecting a partial data from a standard image data, recognizing image based on the selected data, reduction-converting the selected data, and recognizing image based on the reduction-converted data.

摘要翻译： 提供一种图像识别方法。 图像识别方法包括从标准图像数据中选择部分数据，基于所选择的数据识别图像，减少所选数据的转换，以及基于缩小转换数据识别图像。

公开(公告)号：US20120081542A1

公开(公告)日：2012-04-05

申请号：US13179122

申请日：2011-07-08

申请人： Jung Hee SUK ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Wook Jin Chung ,  Jeong Hwan Lee ,  Jae Chang Shim ,  Tae Moon Roh

发明人： Jung Hee SUK ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Wook Jin Chung ,  Jeong Hwan Lee ,  Jae Chang Shim ,  Tae Moon Roh

IPC分类号： H04N7/18 ,  G06K9/00

CPC分类号： H04N7/181 ,  G06K9/00805

摘要： The obstacle detecting system includes a first image acquiring unit which acquires first image information by selectively receiving a laser beam emitted from at least one laser source toward a road surface at a target distance; a second image acquiring unit which acquires an image of actual surroundings as second image information; an image recognizing unit which recognizes an image of an obstacle by performing 3-D image recognition signal processing on line information of the laser beam using the first image information, and recognizes a pattern of the obstacle by performing pattern recognition signal processing on the second image information; and a risk determining unit which determines a possibility of collision due to presence of the obstacle within the target distance by classifying the recognized obstacles according to whether or not the image-recognized obstacle is matched with the pattern-recognized obstacle.

摘要翻译： 障碍物检测系统包括第一图像获取单元，其通过从目标距离选择性地接收从至少一个激光源发射到路面的激光束来获取第一图像信息; 第二图像获取单元，其获取实际环境的图像作为第二图像信息; 图像识别单元，其通过使用第一图像信息对激光束的线信息进行3-D图像识别信号处理来识别障碍物的图像，并且通过对第二图像执行模式识别信号处理来识别障碍物的图案 信息; 以及风险确定单元，其根据图像识别的障碍物是否与图案识别的障碍物匹配，通过对所识别的障碍物进行分类来确定由于目标距离内的障碍物的存在引起的碰撞的可能性。

公开(公告)号：US07958179B2

公开(公告)日：2011-06-07

申请号：US11978878

申请日：2007-10-30

申请人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： G06F7/38

CPC分类号： G06F7/57

摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

摘要翻译： 提供了可重构处理器的算术方法和装置。 算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从ALU，乘法器和移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

公开(公告)号：US20080140745A1

公开(公告)日：2008-06-12

申请号：US11978878

申请日：2007-10-30

申请人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： G06F5/01

CPC分类号： G06F7/57

摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

摘要翻译： 提供了可重构处理器的算术方法和装置。 算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从所述ALU，所述乘法器和所述移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

公开(公告)号：US06636435B2

公开(公告)日：2003-10-21

申请号：US10032987

申请日：2001-12-27

申请人： Yil Suk Yang ,  Tae Moon Roh ,  Jong Dae Kim ,  Byoung Gon Yu

发明人： Yil Suk Yang ,  Tae Moon Roh ,  Jong Dae Kim ,  Byoung Gon Yu

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： The present invention relates to a ferroelectric memory cell array formed of a single transistor, and method of storing data using the same. The ferroelectric memory cell array includes a plurality of word lines connected to gates of the memory cells located at respective rows, a plurality of bit lines connected to drains of the memory cells located at respective columns, a common source line commonly connecting sources of the memory cells, and a plurality of well lines each connected to wells in which the memory cells are each formed, wherein a bias voltage of an unit pulse shape is applied to a gate of a selected memory cell and a bias voltage of a pulse shape is applied to a well line. Therefore, the present invention allows a random access without a disturbance since data can be written by means of the polarity characteristic of the ferroelectric.

摘要翻译： 本发明涉及由单个晶体管形成的铁电存储单元阵列，以及使用该晶体管存储数据的方法。 铁电存储单元阵列包括连接到位于各行的存储单元的栅极的多条字线，连接到位于相应列的存储单元的漏极的多个位线，通常连接存储器的源极的公共源极线 单元和多个井管线，每个阱管线连接到其中形成有存储单元的阱，其中单位脉冲形状的偏置电压被施加到所选存储单元的栅极并施加脉冲形状的偏置电压 到一条井线 因此，本发明允许无障碍地随机存取，因为可以通过铁电体的极性特性写入数据。

公开(公告)号：US07721038B2

公开(公告)日：2010-05-18

申请号：US12171397

申请日：2008-07-11

申请人： Ik Jae Chun ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Ik Jae Chun ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1657 ,  G06F13/28

摘要： Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access.

摘要翻译： 提供了一种用于多媒体系统的片上系统（SoC）系统，能够高速传输大量的多媒体数据和处理器来快速控制外围设备。 SoC系统包括一个处理器; 多个外围设备; 多个物理划分的存储器; 用于将控制信号从处理器传送到外围设备和存储器的控制总线; 用于在处理器，外围设备和存储器之间传送数据的数据总线; 用于将控制总线和数据总线耦合到处理器的桥; 耦合到控制总线并控制每个存储器的多个存储器控制器; 耦合到数据总线和控制总线的直接存储器访问（DMA）控制器，并控制外围设备和存储器之间的数据传输; 以及耦合在DMA控制器和存储器控制器之间的矩阵开关，并且能够同时进行多个存储器访问。

公开(公告)号：US20060105528A1

公开(公告)日：2006-05-18

申请号：US11182671

申请日：2005-07-15

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/66659

摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

摘要翻译： 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。 在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。 此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。 此外，由于异质结构造成的垂直电场的减少导致跨导增益（Gm），结果是热电子效应被抑制，并且器件的可靠性增强。