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    Topography compensating land grid array interposer
    42.
    发明申请
    Topography compensating land grid array interposer 失效
    地形补偿地面阵列插值器

    公开(公告)号：US20100173505A1

    公开(公告)日：2010-07-08

    申请号：US12462985

    申请日：2009-08-11

    申请人： Gareth G. Hougham ,  Brian S. Beaman ,  John S. Corbin ,  Paul Coteus ,  Shawn A. Hall ,  Kathleen C. Hinge ,  Theron L. Lewis ,  Frank R. Libsch ,  Amanda E. E. Mikhail

    发明人： Gareth G. Hougham ,  Brian S. Beaman ,  John S. Corbin ,  Paul Coteus ,  Shawn A. Hall ,  Kathleen C. Hinge ,  Theron L. Lewis ,  Frank R. Libsch ,  Amanda E. E. Mikhail

    IPC分类号： H01R12/14 ,  H01R13/22 ,  H01R43/00

    CPC分类号： H05K3/368 ,  H01R12/52 ,  H01R12/714 ,  H05K1/0269 ,  H05K3/325 ,  H05K2201/10378 ,  Y10T29/49117 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

    摘要： LGA connectors are fabricated with buttons or spring contacts preformed to different heights to accommodate the initial topography of a typical module or PCB of a particular product type. This is accomplished during fabrication by measuring topographies of mating surfaces of a first electronic device and of a second electronic device; fabricating interposer contacts to form opposing non-planar sides having respective inverse topographies for contacting the mating surfaces; and sandwiching the interposer between the first and second electronic devices with the opposing sides in contact with respective mating surfaces. For those LGA types made by molding techniques such as the metal-in-polymer type (eg. Tyco Electronics MPI, or Shin Etsu RP) or the Metal-on-Elastomer type (IBM), using molds with the desired topography provides the desired LGA topography. For those LGAs made of metal springs, cantilevers, armatures and the like, the desired topography is imposed by shaping of the buttons during or after fabrication using a sizing die with the desired topography.

    摘要翻译： LGA连接器采用预制到不同高度的按钮或弹簧触点制成，以适应特定产品类型的典型模块或PCB的初始形貌。 这是通过测量第一电子装置和第二电子装置的配合表面的形貌来制造的; 制造内插器触点以形成具有用于接触配合表面的相应反向形状的相对非平面侧; 并且将所述插入件夹在所述第一和第二电子设备之间，所述相对侧与相应的配合表面相接触。 对于通过成型技术（例如，Tyco Electronics MPI或Shin Etsu RP）或Metal-on-Elastomer型（IBM）的成型技术制造的LGA类型，使用具有所需形貌的模具提供所需的 LGA地形。 对于由金属弹簧，悬臂，电枢等制成的那些LGAs，通过使用具有所需形状的尺寸模具在制造期间或之后使按钮成形来施加所需的形状。

    OPTIMIZED SCALABLE NETWORK SWITCH
    44.
    发明申请
    OPTIMIZED SCALABLE NETWORK SWITCH 失效
    优化可调网络交换机

    公开(公告)号：US20080091842A1

    公开(公告)日：2008-04-17

    申请号：US11868223

    申请日：2007-10-05

    申请人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus

    发明人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus

    IPC分类号： G06F15/173

    CPC分类号： H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338

    摘要： In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2 m plurality of compact bit vectors containing information derived from downstream nodes. A multilevel arbitration process in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers, is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors. This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.

    摘要翻译： 在具有多维配置的多个节点的大规模并行计算系统中，每个节点包括计算设备，用于将分组路由到其目的地节点的方法，包括生成2m个紧凑位中的至少一个 包含从下游节点导出的信息的向量。 存储在紧凑向量中的下行信息（诸如链路状态信息和下游缓冲器的丰满度）的多级仲裁过程被用于确定分组传输的优选方向和虚拟信道。 优选的方向范围被编码，并且通过检查多个紧凑比特向量来选择虚拟信道。 这种动态路由方法消除了路由表的必要性，从而增强了交换机的可扩展性。

    STRUCTURE COMPRISING 3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, CIRCUIT STRUCTURE, AND INSTRUCTIONS FOR FABRICATION THEREOF
    45.
    发明申请
    STRUCTURE COMPRISING 3-DIMENSIONAL INTEGRATED CIRCUIT ARCHITECTURE, CIRCUIT STRUCTURE, AND INSTRUCTIONS FOR FABRICATION THEREOF 有权
    包含三维集成电路结构的结构，电路结构及其制造说明

    公开(公告)号：US20070283298A1

    公开(公告)日：2007-12-06

    申请号：US11768210

    申请日：2007-06-26

    申请人： Kerry Bernstein ,  Paul Coteus ,  Philip Emma

    发明人： Kerry Bernstein ,  Paul Coteus ,  Philip Emma

    IPC分类号： G06F17/50

    CPC分类号： H01L21/6835 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L2221/68359 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105

    摘要： A design structure comprising an integrated circuit architecture, circuit structure, and/or instructions for fabrication thereof. The circuit structure includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

    摘要翻译： 一种包括集成电路架构，电路结构和/或其制造指令的设计结构。 电路结构包括至少一个逻辑器件层和至少两个另外的分离的存储器阵列层。 对于设置在其中的特定类型的逻辑设备或存储器件，逻辑器件层和至少两个存储器阵列层中的每一个被独立地优化。 优选地还设置在逻辑器件层内的是阵列读出放大器，存储器阵列输出驱动器和类似的高性能电路，否则通常设置在存储器阵列层衬底内。 所有层可以独立供电以提供额外的性能增强。

    METHOD AND SYSTEM FOR PROVIDING INDETERMINATE READ DATA LATENCY IN A MEMORY SYSTEM
    47.
    发明申请
    METHOD AND SYSTEM FOR PROVIDING INDETERMINATE READ DATA LATENCY IN A MEMORY SYSTEM 审中-公开
    用于在存储器系统中提供读取数据延迟的方法和系统

    公开(公告)号：US20070183331A1

    公开(公告)日：2007-08-09

    申请号：US11736196

    申请日：2007-04-17

    申请人： Paul Coteus ,  Kevin Gower ,  Warren Maule ,  Robert Tremaine

    发明人： Paul Coteus ,  Kevin Gower ,  Warren Maule ,  Robert Tremaine

    IPC分类号： H04J1/16

    CPC分类号： G06F13/1657 ,  G06F13/1673

    摘要： A method and system for providing indeterminate read data latency in a memory system. The method includes determining if a local data packet has been received. If a local data packet has been received, then the local data packet is stored into a buffer device. The method also includes determining if the buffer device contains a data packet and determining if an upstream driver for transmitting data packets to a memory controller via an upstream channel is idle. If the buffer contains a data packet and the upstream driver is idle, then the data packet is transmitted to the upstream driver. The method further includes determining if an upstream data packet has been received. The upstream data packet is in a frame format that includes a frame start indicator and an identification tag for use by the memory controller in associating the upstream data packet with its corresponding read instruction. If an upstream data packet has been received and the upstream driver is not idle, then the upstream data packet is stored into the buffer device. If an upstream data packet has been received and the buffer device does not contain a data packet and the upstream driver is idle, then the upstream data packet is transmitted to the upstream driver. If the upstream driver is not idle, then any data packets in progress are continued being transmitted to the upstream driver.

    摘要翻译： 一种用于在存储器系统中提供不确定的读取数据等待时间的方法和系统。 该方法包括确定是否已经接收到本地数据分组。 如果接收到本地数据分组，则本地数据分组被存储到缓冲设备中。 该方法还包括确定缓冲器装置是否包含数据包，并确定是否经由上游信道将数据包发送到存储器控制器的上行驱动器空闲。 如果缓冲区包含数据包，并且上游驱动程序处于空闲状态，则将数据包传送到上游驱动程序。 该方法还包括确定是否已经接收到上游数据分组。 上行数据包是帧格式，包括帧开始指示符和存储器控制器在将上行数据包与其对应的读取指令相关联时使用的识别标签。 如果已经接收到上游数据分组，并且上游驱动程序不空闲，则上游数据分组被存储到缓冲设备中。 如果已经接收到上游数据分组，并且缓冲设备不包含数据分组，并且上游驱动器空闲，则将上游数据分组发送到上游驱动程序。 如果上游驱动程序不空闲，那么正在进行的任何数据分组都将继续传输到上游驱动程序。

    Methods and apparatus using commutative error detection values for fault isolation in multiple node computers
    48.
    发明申请
    Methods and apparatus using commutative error detection values for fault isolation in multiple node computers 失效
    使用多节点计算机故障隔离交换误差检测值的方法和装置

    公开(公告)号：US20060248370A1

    公开(公告)日：2006-11-02

    申请号：US11106069

    申请日：2005-04-14

    申请人： Gheorghe Almasi ,  Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Sarabjeet Singh ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    发明人： Gheorghe Almasi ,  Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Sarabjeet Singh ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1633

    摘要： The present invention concerns methods and apparatus for performing fault isolation in multiple node computing systems using commutative error detection values—for example, checksums—to identify and to isolate faulty nodes. In the present invention nodes forming the multiple node computing system are networked together and during program execution communicate with one another by transmitting information through the network. When information associated with a reproducible portion of a computer program is injected into the network by a node, a commutative error detection value is calculated and stored in commutative error detection apparatus associated with the node. At intervals, node fault detection apparatus associated with the multiple node computer system retrieve commutative error detection values saved in the commutative error detection apparatus associated with the node and stores them in memory. When the computer program is executed again by the multiple node computer system, new commutative error detection values are created; the node fault detection apparatus retrieves them and stores them in memory. The node fault detection apparatus identifies faulty nodes by comparing commutative error detection values associated with reproducible portions of the application program generated by a particular node from different runs of the application program. Differences in commutative error detection values indicate that the node may be faulty.

    摘要翻译： 本发明涉及在多节点计算系统中使用交换性错误检测值（例如校验和）识别和隔离故障节点来执行故障隔离的方法和装置。 在本发明中，形成多节点计算系统的节点被联网在一起，并且在程序执行期间通过网络传送信息彼此通信。 当与计算机程序的可再现部分相关联的信息被节点注入到网络中时，计算交换性错误检测值并将其存储在与节点相关联的交换错误检测装置中。 间歇地，与多节点计算机系统相关联的节点故障检测装置检索保存在与节点相关联的交换性错误检测装置中的交换性错误检测值，并将其存储在存储器中。 当多节点计算机系统再次执行计算机程序时，创建新的交换错误检测值; 节点故障检测装置检索它们并将其存储在存储器中。 节点故障检测装置通过比较与来自应用程序的不同运行的特定节点生成的应用程序的可再现部分相关联的交换错误检测值来识别故障节点。 交换性错误检测值的差异表明节点可能有故障。

    Elastic interface for master-slave communication
    50.
    发明授权
    Elastic interface for master-slave communication 有权
    用于主从通信的弹性接口

    公开(公告)号：US06571346B1

    公开(公告)日：2003-05-27

    申请号：US09434800

    申请日：1999-11-05

    申请人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Bradley McCredie ,  Paul Coteus

    发明人： Daniel Mark Dreps ,  Frank David Ferraiolo ,  Kevin Charles Gower ,  Bradley McCredie ,  Paul Coteus

    IPC分类号： G06F104

    CPC分类号： G06F5/06

    摘要： A method and apparatus are disclosed for communicating between a master and slave device. A sequence of data sets and a clock signal (“Bus clock”) are sent from the master to the slave, wherein the successive sets are asserted by the master at a certain frequency, each set being asserted for a certain time interval. The data and Bus clock are received by the slave, including capturing the data by the slave, responsive to the received Bus clock. The slave generates, from the received Bus clock, a clock (“Local clock”) for clocking operations on the slave. The sequence of the received data sets is held in a sequence of latches in the slave, each set being held for a time interval that is longer than the certain time interval for which the set was asserted by the master. The data sets are read in their respective sequence from the latches, responsive to the Local clock, so that the holding of respective data sets for the relatively longer time intervals in multiple latches and the reading of the data in sequence increases allowable skew of the Local clock relative to the received Bus clock.

    摘要翻译： 公开了用于在主设备和从设备之间进行通信的方法和设备。 一系列数据组和时钟信号（“总线时钟”）从主机发送到从机，其中连续组由主机以某一频率断言，每组都被断言一段时间间隔。 数据和总线时钟由从机接收，包括响应于接收的总线时钟由从机捕获数据。 从器件从接收的总线时钟产生一个时钟（“本地时钟”），用于在从机上进行时钟操作。 所接收的数据集的序列被保持在从属序列中的锁存器序列中，每个集合被保持一段时间间隔，该时间间隔长于由主机确定该集合的特定时间间隔。 响应于本地时钟，从锁存器读取它们各自的序列中的数据集，使得在多个锁存器中相对较长的时间间隔保持相应的数据集并且依次读取数据增加本地 时钟相对于接收的总线时钟。