INTEGRATED CIRCUITS WITH VERTICAL JUNCTIONS BETWEEN nFETS AND pFETS, AND METHODS OF MANUFACTURING THE SAME
    41.
    发明申请
    INTEGRATED CIRCUITS WITH VERTICAL JUNCTIONS BETWEEN nFETS AND pFETS, AND METHODS OF MANUFACTURING THE SAME 审中-公开
    具有nFET和pFET之间的垂直结的集成电路及其制造方法

    公开(公告)号:US20150357433A1

    公开(公告)日:2015-12-10

    申请号:US14299829

    申请日:2014-06-09

    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an implant mask overlying a dummy gate, where the implant mask produces a masked dummy gate and an exposed dummy gate. Ions are implanted into the exposed dummy gate, and the implant mask is removed. The masked dummy gate is etched with an etchant selective to the masked dummy gate over the exposed dummy gate to form a trench, and the trench is filled with a conductive material.

    Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括形成覆盖在虚拟栅极上的注入掩模,其中所述注入掩模产生掩蔽的伪栅极和暴露的伪栅极。 将离子注入暴露的虚拟栅极中,并移除植入物掩模。 用掩蔽的伪栅极对暴露的伪栅极选择性地蚀刻掩蔽的虚拟栅极以形成沟槽,并且沟槽填充有导电材料。

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