公开(公告)号：US20070294327A1

公开(公告)日：2007-12-20

申请号：US11894393

申请日：2007-08-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G06F7/58

CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

公开(公告)号：US06557129B1

公开(公告)日：2003-04-29

申请号：US09619988

申请日：2000-07-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R3128

CPC分类号： G01R31/318547

摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

公开(公告)号：US06539409B2

公开(公告)日：2003-03-25

申请号：US09957701

申请日：2001-09-18

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G06F102

CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

公开(公告)号：US08533547B2

公开(公告)日：2013-09-10

申请号：US13013712

申请日：2011-01-25

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

公开(公告)号：US20110055646A1

公开(公告)日：2011-03-03

申请号：US12678747

申请日：2008-09-18

申请人： Nilanjan Mukherjee ,  Artur Pogiel ,  Janusz Rajski ,  Jerzy Tyszer

发明人： Nilanjan Mukherjee ,  Artur Pogiel ,  Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G11C29/12 ,  G06F11/27

CPC分类号： G11C29/56 ,  G11C29/40 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/1208

摘要： Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self-test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feed-back structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter (211), a failing column indicator (213), and/or a failing row indicator (214) to collect memory location information for a failing test response.

摘要翻译： 公开的是用于在存储器内置自检环境中暂时压缩失败存储器测试的测试响应签名的方法和设备，以提供即使在多个时间相关存储器的检测中进行存储器内置自检操作的能力 测试失败。 在本发明的一些实施方案中，将压实的测试响应签名与存储器位置信息一起提供给自动测试设备设备。 根据本发明的各种实施方式，具有嵌入式存储器（204）和存储器BIST控制器（206）的集成电路还包括用作签名寄存器的线性反馈结构（410），其可以临时压缩来自 在内存测试的测试步骤中的嵌入式存储器阵列。 在各种实现中，集成电路还可以包括故障字计数器（211），故障列指示器（213）和/或故障行指示器（214），以收集故障测试响应的存储器位置信息。

公开(公告)号：US07805649B2

公开(公告)日：2010-09-28

申请号：US12396377

申请日：2009-03-02

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G01R31/318547

摘要： A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.

摘要翻译： 一种在确定性测试环境中压缩包含未知值或多个故障效应的测试响应的方法和装置。 所提出的选择性压实机采用具有用于选择性地将测试响应传递给压实机的选择电路的线性压实机。 在一个实施例中，门控逻辑由控制寄存器，解码器和标志寄存器控制。 该电路结合任何常规的并行测试响应压缩方案，允许控制电路选择性地使所需扫描链的串行输出以特定时钟速率馈送到并联压实机。 第一个标志寄存器确定是否启用所有或只有一些扫描链输出并通过压实器馈送。 第二个标志寄存器确定选择器寄存器选择的扫描链是否启用，所有其他扫描链是禁用的，还是禁用所选扫描链，并启用所有其他扫描链。 其他实施例允许对可变数目的扫描链输出的选择性掩蔽。

公开(公告)号：US20090183041A1

公开(公告)日：2009-07-16

申请号：US12352994

申请日：2009-01-13

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318335 ,  G01R31/31813 ,  G01R31/318547

摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

摘要翻译： 在测试电路中将测试图案应用于扫描链的方法。 该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。 取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。 执行解压缩的电路包括解压缩器，例如适于接收压缩的比特测试模式的线性反馈状态机。 解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。 电路还包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并且适于接收解压缩的测试图案。

公开(公告)号：US20090177933A1

公开(公告)日：2009-07-09

申请号：US12402880

申请日：2009-03-12

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318335 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547

摘要： A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

摘要翻译： 微芯片上的新型解压缩器/ PRPG对芯片上的电路不足测试的确定性测试模式进行伪随机测试模式生成和解压缩。 解压缩器/ PRPG有两个操作阶段。 在伪随机阶段，解压缩器/ PRPG生成伪随机测试图案，其应用于被测电路中的扫描链。 在确定性阶段，将外部测试仪的压缩确定性测试模式应用于解压缩器/ PRPG。 在通过解压缩器/ PRPG计时到扫描链中时，模式被解压缩。 因此，解压缩器/ PRPG提供比简单PRPG更好的故障覆盖，但是没有完整的完整指定的确定性测试模式的成本。

公开(公告)号：US20070234163A1

公开(公告)日：2007-10-04

申请号：US11709079

申请日：2007-02-20

申请人： Nilanjan Mukherjee ,  Janusz Rajski ,  Jerzy Tyszer

发明人： Nilanjan Mukherjee ,  Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G06F11/00 ,  G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G01R31/318563 ,  G01R31/318566

摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

摘要翻译： 这里公开了所谓的“X-press”测试响应压实机的示例性实施例。 所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。 所公开技术的某些实施例提供约1000x的压实比。 所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。 扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。 本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

公开(公告)号：US20070016836A1

公开(公告)日：2007-01-18

申请号：US11523111

申请日：2006-09-18

申请人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Mark Kassab ,  Nilanjan Mukherjee ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G01R31/318335 ,  G01R31/318371 ,  G01R31/318547

摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test. Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit. A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell. The equations are solved to obtain the compressed test pattern.

摘要翻译： 一种用于压缩被测电路中扫描链应用的测试图案的方法。 该方法包括生成与扫描链内的扫描单元相关联的符号表达式。 通过将变量分配给提供给被测电路的外部输入通道上的位来创建符号表达式。 使用符号仿真，将变量应用于解压缩器以获取符号表达式。 使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障。 通过将测试立方体中的分配值与与相应扫描单元相关联的符号表达式进行等价来表示一组方程式。 求解等式以获得压缩测试图案。