摘要:
In particular embodiments, a method includes accessing first binary decision diagrams (BDDs) representing data streams from sensors, selecting portions from the first BDDs based on ease-of-analysis, and constructing a second BDD by performing an OR operation between the selected portions of the first BDDs.
摘要:
One embodiment accesses a binary decision diagram (BDD) representing a function having n variables; constructs one group of one ordered set of the n variables; recursively constructs one or more new groups of one or more ordered sets of one or more variables, replacing existing groups of one or more ordered sets of one or more variables, until each existing group comprises one or more ordered sets of k variables or less, where 1≦k
摘要翻译:一个实施例访问表示具有n个变量的函数的二进制决策图(BDD); 构造一组n个变量的一个有序集合; 递归地构造一个或多个变量的一个或多个有序集合的一个或多个新组,替换一个或多个变量的一个或多个有序集合的现有组,直到每个现有组包括k个变量的一个或多个有序集合或更少, 其中1≦̸ k
摘要:
A method for processing access control lists using a hashing scheme includes receiving a packet identifying data and determining a fixed number of a plurality of hash tables comprising a fixed number of two or more buckets comprising a fixed number of one or more entries, such that the two or more hash tables store data in memory associated with an access control list. The method also includes searching the one or more hash tables in parallel for the identifying data using a plurality of hashing functions and returning a search result.
摘要:
One embodiment accesses a binary decision diagram (BDD) representing a function having n variables, where n≧2, wherein: the BDD comprises n layers corresponding to the n variables, respectively; and the BDD has a first variable order where each variable i is at layer i for 1≦i≦n; and reorders the n variables of the BDD according to a second variable order denoted as π(i), where each variable i is at layer π(i) for 1≦i≦n, by iteratively and alternatingly swapping one or more first disjoint pairs of consecutive layers during each odd iteration and swapping one or more second disjoint pairs of consecutive layers during each even iteration, until the second variable order is achieved, wherein during each iteration, two consecutive layers are swapped only if a current order of two variables at the two consecutive layers differs from an order of the two variables specified by the second variable order.
摘要:
In one embodiment, generating an ontology includes accessing an inverted index comprising a plurality of inverted index lists. An inverted index list may correspond to a term of a language. Each inverted index list may comprise a term identifier of the term and one or more document identifiers indicating one or more documents of a document set in which the term appears. The embodiment also includes generating a term identifier index according to the inverted index. The term identifier index comprises a plurality of sections and each section corresponds to a document. Each section may comprise one or more term identifiers of one or more terms that appear in the document.
摘要:
A method includes receiving input data comprising a plurality of bits and processing an access control list into an ESOP expression comprising a plurality of product terms. The method also includes storing a plurality of bits associated with the plurality of product terms in a TCAM comprising a plurality of rows and comparing the plurality of bits associated with the input data to the plurality of bits associated with the product terms stored in each row of the plurality of rows, such that each row of the TCAM outputs a plurality of signals, such that each of the plurality of signals indicate a match or no match for each bit stored in the selected row. The method includes receiving the plurality of signals from the plurality of rows by an ESOP evaluator and outputting an address associated with a selected row from the plurality of rows of the TCAM.
摘要:
In one embodiment, a method for validating one or more circuits using one or more grids includes accessing a circuit and generating one or more seeds for executing one or more instances of validation on the circuit. Each instance of validation comprising one or more tasks. The method also includes distributing the tasks and the seeds across a grid including multiple nodes and, using the seeds, executing the instances of validation at the nodes in the grid according to the tasks.
摘要:
In one embodiment, a method for multithreaded reachability analysis includes partitioning a state space of a circuit under analysis into a plurality of partitions and assigning each partition to a thread to carry out a reachability analysis on the partition assigned to the thread. The threads carry out the reachability analyses of the partitions in parallel with each other. The method also includes using one or more of an early communication algorithm and a partial communication algorithm to communicate states from one or more first ones of the partitions to one or more second ones of the partitions to facilitate the reachability analysis of the second ones of the partitions.
摘要:
In one embodiment, a method for determining one or more reachable states in a circuit using distributed computing and one or more partitioned data structures includes, at a first one of multiple computing systems, receiving a first partition of a circuit. The first partition corresponds to a first binary decision diagram (BDD) having a first density. The method includes performing a first reachability analysis on the first partition using the first BDD until a fixed point in the first partition has been reached and, if, during the first reachability analysis, the size of the first BDD exceeds a threshold, discarding the first BDD. The method includes communicating with at least one second one of the multiple computing systems. The second one of the multiple computing systems has received a second partition of the circuit. The second one of the multiple computing systems has performed a second reachability analysis on the second BDD without discarding the second BDD.
摘要:
A system and method for representing digital circuits and systems in multiple partitions of Boolean space, and for performing digital circuit or system validation using the multiple partitions. Decision diagrams are built for the digital circuit or system and pseudo-variables are introduced at decomposition points to reduce diagram size. Pseudo-variables remaining after decomposition are composed and partitioned to represent the digital circuit or system as multiple partitions of Boolean space. Each partition is built in a scheduled order, and is manipulable separately from other partitions.