利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

70 条记录 (耗时 0.06 秒)

    Capacitor charging sensor
    42.
    发明授权
    Capacitor charging sensor 失效
    电容充电传感器

    公开(公告)号：US06144037A

    公开(公告)日：2000-11-07

    申请号：US99602

    申请日：1998-06-18

    申请人： James G. Ryan ,  Badih El-Kareh ,  Auguste B. El-Kareh

    发明人： James G. Ryan ,  Badih El-Kareh ,  Auguste B. El-Kareh

    IPC分类号： G01Q70/00 ,  H01J37/02 ,  H01J37/304

    CPC分类号： H01J37/304 ,  H01J37/026 ,  H01J2237/244

    摘要： A system for detecting charge accumulation during semiconductor wafer manufacturing including a sensor comprising a capacitor, an emitter for directing a primary electron beam toward the sensor, wherein the primary electron beam causes the sensor to emit secondary electrons and a detector for measuring the secondary electrons.

    摘要翻译： 一种用于检测半导体晶片制造期间的电荷累积的系统，包括：传感器，包括电容器，用于将一次电子束朝向传感器引导的发射器，其中所述一次电子束使所述传感器发射二次电子;以及用于测量所述二次电子的检测器。

    Method for dual gate oxide dual workfunction CMOS
    43.
    发明授权
    Method for dual gate oxide dual workfunction CMOS 失效
    双栅氧化双功函数CMOS方法

    公开(公告)号：US06087225A

    公开(公告)日：2000-07-11

    申请号：US18939

    申请日：1998-02-05

    申请人： Gary Bela Bronner ,  Badih El-Kareh ,  Stanley Everett Schuster

    发明人： Gary Bela Bronner ,  Badih El-Kareh ,  Stanley Everett Schuster

    IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10873 ,  H01L21/823842

    摘要： A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO.sub.2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.

    摘要翻译： 在同一芯片上形成包括两个不同类型的NFET和/或两个不同类型的PFET的集成电路芯片的方法，例如厚和薄栅极氧化物FET。 DRAM阵列可以由厚氧化物FET构成，并且逻辑电路可以由同一芯片上的薄氧化物FET构成。 首先，在晶片上形成包括第一厚栅极SiO 2层的栅极堆叠。 堆叠包括栅极氧化物层上的掺杂多晶硅层，多晶硅层上的硅化物层和硅化物层上的氮化物层。 选择性地去除堆叠的一部分以重新暴露将要形成逻辑电路的晶片。 在再曝光的晶片上形成更薄的栅氧化层。 接下来，在较薄的栅极氧化物层上形成栅极，并且在栅极处形成薄氧化物NFET和PFET。 在选择性硅化薄氧化物器件区域之后，在厚氧化物器件区域中从堆叠中蚀刻栅极。 最后，源极和漏极区域被注入并扩散用于厚栅极氧化物器件。

    Floating gate interlevel defect monitor and method
    44.
    发明授权
    Floating gate interlevel defect monitor and method 失效
    浮栅层间缺陷监测和方法

    公开(公告)号：US5889410A

    公开(公告)日：1999-03-30

    申请号：US652216

    申请日：1996-05-22

    申请人： Badih El-Kareh ,  Stephen Parke

    发明人： Badih El-Kareh ,  Stephen Parke

    IPC分类号： H01L23/544 ,  G01R31/26

    CPC分类号： H01L22/34 ,  H01L2924/0002

    摘要： According to the preferred embodiment, a defect monitor is provided that uses a floating gate structure. The defect monitor includes a common source, a common drain, and a plurality of floating gates interdispersed between the source and drain. Additionally, a conductor covers the plurality of floating gates. By applying a bias to the conductor and measuring the current flowing through the drain and source, the distribution of defects on the semiconductor wafer can be estimated.

    摘要翻译： 根据优选实施例，提供了使用浮动栅极结构的缺陷监视器。 缺陷监视器包括公共源，公共漏极和分散在源极和漏极之间的多个浮动栅极。 另外，导体覆盖多个浮动栅极。 通过向导体施加偏压并测量流过漏极和源极的电流，可以估计半导体晶片上的缺陷分布。

    Trench capacitor structures
    45.
    发明授权
    Trench capacitor structures 失效

    公开(公告)号：US5805494A

    公开(公告)日：1998-09-08

    申请号：US846603

    申请日：1997-04-30

    申请人： Badih El-Kareh ,  Richard Leo Kleinhenz ,  Stanley Everett Schuster

    发明人： Badih El-Kareh ,  Richard Leo Kleinhenz ,  Stanley Everett Schuster

    IPC分类号： H01L27/108 ,  H01L27/11 ,  H01L29/94 ,  G11C11/24

    CPC分类号： H01L29/945 ,  H01L27/10829 ,  H01L27/1104 ,  Y10S257/903

    摘要： An optimized trench capacitor structure which is useful as a decoupling capacitor or a storage capacitor can be manufactured without added process complexity. As an on-chip decoupling trench capacitor structure, the structure reduces the series resistance to outer and inner plates and results in an acceptable RC delay, while maintaining a high capacitance per unit area. As a storage capacitor with a buried shield, the trench capacitor structure exhibits high immunity to alpha particle and cosmic radiation induced failures. The trench capacitor structure which includes a buried n-well in a silicon substrate. A trench is formed in the substrate and extends through the buried n-well. A dielectric film is formed on an inner surface of the trench, and an inner plate formed as a polysilicon fill within the trench is connected to a surface n+ film formed during definition of peripheral source/drain contacts of the integrated circuit. An outer plate of the capacitor in the form of an out diffusion from the trench provides a low resistance electrical contact with the substrate. A number of these capacitors can be combined in a very efficient X-Y array of decoupling capacitors.

    ESD structure that employs a schottky-barrier to reduce the likelihood of latch-up
    46.
    发明授权
    ESD structure that employs a schottky-barrier to reduce the likelihood of latch-up 失效
    使用肖特基势垒的ESD结构减少闭锁的可能性

    公开(公告)号：US5763918A

    公开(公告)日：1998-06-09

    申请号：US740134

    申请日：1996-10-22

    申请人： Badih El-Kareh ,  James Gardner Ryan ,  Hiroyoshi Tanimoto

    发明人： Badih El-Kareh ,  James Gardner Ryan ,  Hiroyoshi Tanimoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/092 ,  H01L29/47 ,  H01L29/872 ,  H01L23/62

    CPC分类号： H01L27/0255 ,  H01L2924/0002

    摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to decrease the latch-up susceptibility of an ESD structure by suppressing the injection of minority carriers that cause transistor action to occur. This is accomplished, for example, by using a metal contact to the n-substrate or n-well in place of or in parallel with the prior art p-diffusion. Using such a metal contact forms a Schottky Barrier Diode (SBD) with the ESD structure. Since the SBD is a majority-carrier device, negligible minority carriers are injected when the SBD is in forward bias, thereby reducing the likelihood of latch-up.

    摘要翻译： 本发明的优选实施例克服了现有技术的局限，并且提供了一种通过抑制引起晶体管作用发生的少数载流子的注入来减小ESD结构的闭锁敏感性的装置和方法。 这是通过例如通过使用与n衬底或n阱的金属接触来代替或与现有技术的p-扩散并行来实现的。 使用这种金属接触形成具有ESD结构的肖特基势垒二极管（SBD）。 由于SBD是多数载波器件，当SBD处于正向偏置时，可以忽略少数载流子，从而降低闩锁的可能性。

    Systems, methods and devices for a memory having a buried select line
    48.
    发明授权
    Systems, methods and devices for a memory having a buried select line 有权
    具有掩埋选择线的存储器的系统，方法和装置

    公开(公告)号：US08530952B2

    公开(公告)日：2013-09-10

    申请号：US11895505

    申请日：2007-08-23

    申请人： Badih El-Kareh

    发明人： Badih El-Kareh

    IPC分类号： H01L29/788

    CPC分类号： G11C16/10 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/06 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11524

    摘要： Memory cells and methods for programming and erasing a memory cell by utilizing a buried select line are described. A voltage potential may be generated between a source-drain region and the buried select line region of the memory cell to store charge in a storage region between the source-drain and buried select line regions. The generated voltage potential causes electrons to either tunnel towards the buried storage region to store electrical charge or away from the buried storage region to discharge electrical charge.

    摘要翻译： 描述了通过利用掩埋选择线来编程和擦除存储器单元的存储单元和方法。 可以在源极 - 漏极区域和存储单元的掩埋选择线区域之间产生电压电位，以将电荷存储在源极 - 漏极和埋入选择线区域之间的存储区域中。 所产生的电压电位导致电子向掩埋的存储区域隧道以存储电荷或远离掩埋的存储区域以放电电荷。