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104 条记录 (耗时 0.033 秒)

    DE-FLUORINATION AFTER VIA ETCH TO PRESERVE PASSIVATION
    42.
    发明申请
    DE-FLUORINATION AFTER VIA ETCH TO PRESERVE PASSIVATION 失效
    经过灭火后进行灭火

    公开(公告)号：US20060099785A1

    公开(公告)日：2006-05-11

    申请号：US10904432

    申请日：2004-11-10

    申请人： Nicholas Fuller ,  Timothy Dalton

    发明人： Nicholas Fuller ,  Timothy Dalton

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76807 ,  H01L21/02063

    摘要： Novel interconnect structures possessing a dense OSG material for 90 nm and beyond BEOL technologies in which a low power density oxygen-based de-fluorination plasma process is utilized to increase NBLoK selectivity are presented. These BEOL interconnect structures are capable of delivering enhanced reliability and performance due to the reduced risk of Cu exposure and hence electromigration and stress migration related failures. The oxygen based de-fluorination process is such that the plasma conditions employed {low power density ( 100 mT); negligible ion current to wafer surface (applied source frequency only)} facilitate a physical expulsion of residual fluorine present on the chamber walls, wafer surface, and within the via structure; thus, minimizing the extent of NBLoK etching that can occur subsequent to removing polymeric byproducts of via etching.

    摘要翻译： 提出了具有用于90nm以上的致密OSG材料的新型互连结构，并且提出了使用低功率密度氧基脱氟等离子体工艺来提高NBLoK选择性的BEOL技术。 这些BEOL互连结构能够提供增强的可靠性和性能，因为Cu暴露的风险降低，因此电迁移和压力迁移相关故障。 基于氧的脱氟方法是使用等离子体条件{低功率密度（<0.3WCM <-22）; 相对高压（> 100 mT）; 可忽略离子电流到晶片表面（仅施加源频率）}有助于物理排出存在于室壁，晶片表面和通孔结构内的残留氟; 从而最小化在去除通孔蚀刻的聚合物副产物之后可能发生的NBLoK蚀刻的程度。

    Formation of low resistance via contacts in interconnect structures
    45.
    发明申请
    Formation of low resistance via contacts in interconnect structures 审中-公开
    通过互连结构中的触点形成低电阻

    公开(公告)号：US20050064701A1

    公开(公告)日：2005-03-24

    申请号：US10665584

    申请日：2003-09-19

    申请人： Timothy Dalton ,  Stephen Gates

    发明人： Timothy Dalton ,  Stephen Gates

    IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/02063 ,  H01L21/76814

    摘要： A method of fabricating an interconnect structure including the steps of: forming a porous or dense low k dielectric layer on a substrate; forming single or dual damascene etched openings in the low k dielectric; placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and activating at a temperature about −200° C. to about 25° C. Also provided is an interconnect structure having a substrate, a conductive material disposed on the substrate, a porous or dense low k dielectric layer disposed on the conductive material, wherein the low k dielectric layer has a single or dual damascene etched openings that expose a surface of the conductive material, and metallic lines and vias etched onto the low k dielectric layer; wherein the exposed conductive material has been treated with a CCA and activated in the cold to remove oxide, oxygen and carbon containing residues from the surface of the conductive material.

    摘要翻译： 一种制造互连结构的方法，包括以下步骤：在衬底上形成多孔或致密的低k电介质层; 在低k电介质中形成单或双镶嵌蚀刻孔; 将基板放置在温度约-200℃至约25℃的冷卡盘上的处理室中; 向处理室中加入可冷凝清洁剂（CCA），以在衬底上的蚀刻开口内冷凝CCA层; 并且在约-200℃至约25℃的温度下活化。还提供了具有基底，设置在基底上的导电材料，设置在导电材料上的多孔或致密的低k电介质层的互连结构，其中 低k电介质层具有暴露导电材料的表面的单个或双镶嵌蚀刻开口以及蚀刻到低k电介质层上的金属线和通孔; 其中所述暴露的导电材料已经用CCA处理并且在冷中被活化以从所述导电材料的表面去除氧化物，含氧和碳的残余物。

    INTERCONNECT STRUCTURES AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
    46.
    发明申请
    INTERCONNECT STRUCTURES AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT 有权
    无线电集成电路的互连结构和设计结构

    公开(公告)号：US20120292741A1

    公开(公告)日：2012-11-22

    申请号：US13560446

    申请日：2012-07-27

    申请人： Timothy Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    发明人： Timothy Dalton ,  Ebenezer E. Eshun ,  Sarah L. Grunow ,  Zhong-Xiang He ,  Anthony K. Stamper

    IPC分类号： H01L23/522 ,  G06F17/50

    CPC分类号： H01L21/76885 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L27/016 ,  H01L28/20 ,  H01L28/40

    摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

    摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。