公开(公告)号：US5584002A

公开(公告)日：1996-12-10

申请号：US21010

申请日：1993-02-22

申请人： Philip G. Emma ,  Joshua W. Knight ,  Keith N. Langston ,  James H. Pomerene ,  Thomas R. Puzak

发明人： Philip G. Emma ,  Joshua W. Knight ,  Keith N. Langston ,  James H. Pomerene ,  Thomas R. Puzak

IPC分类号： G06F12/08 ,  G11C29/00 ,  G06F11/20

CPC分类号： G11C29/88 ,  G06F12/0864

摘要： A method for addressing data in a cache unit which has a plurality of congruence classes, following a failure which disables one or more of the congruence classes in the cache unit. A plurality of synonym classes are established. A subset of the congruence classes is assigned to each of the synonym classes. Any disabled congruence classes are identified. The synonym class to which the disabled congruence class belongs is identified. An alternate congruence class is selected which belongs to the same synonym class as the disabled congruence class. When a request is received by the cache to store a line of data into the disabled congruence class, the line is stored into the alternate congruence class in response to the request.

摘要翻译： 一种用于在具有多个同余类的高速缓存单元中寻址数据的方法，该故障在禁用高速缓存单元中的一个或多个同余类之后。 建立了多个同义词类。 同余类的一个子集被分配给每个同义词类。 确定任何残疾同侪课程。 识别残疾同伴课所属的同义词类。 选择一个替代同余类，属于与残疾同余类相同的同义词类。 当高速缓存接收到请求以将一行数据存储到禁用的同余类中时，响应于请求将该行存储到备用同余类中。

公开(公告)号：US5333283A

公开(公告)日：1994-07-26

申请号：US784335

申请日：1991-10-29

申请人： Philip G. Emma ,  David R. Kaeli

发明人： Philip G. Emma ,  David R. Kaeli

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/345

CPC分类号： G06F9/30061 ,  G06F9/3844

摘要： A method and apparatus is disclosed for folding the execution of a multi-way branch or switch based upon an operand (e.g.,the block of instructions normally associated with a case statement) into a single instruction. This insulates branch prediction mechanisms from making incorrect predictions that are normally associated with a multi-way branch. A table saves the past history of multi-way branch execution. This table contains three fields: the starting address of a multi-way branch; a value of the operand used to execute that multi-way branch in the past; and the larger target address generated by that multi-way branch in the past when that particular operand value was used. In accordance with one embodiment of this invention, other branch prediction mechanisms (such as a Branch History Table or Decode History Table) are disabled from redirecting instruction fetching during execution of a multi-way branch in an instruction stream.

摘要翻译： 公开了一种用于基于操作数（例如，通常与案例陈述相关联的指令块）将多路分支或交换机的执行折叠成单个指令的方法和装置。 这使得分支预测机制不能做出通常与多路分支相关联的错误预测。 表保存了多路分支执行的过去历史。 该表包含三个字段：多路分支的起始地址; 过去用于执行该多路分支的操作​​数的值; 以及当使用该特定操作数值时，该多路分支在过去生成的较大的目标地址。 根据本发明的一个实施例，在指令流中的多路分支的执行期间禁止其他分支预测机制（诸如分支历史表或解码历史表）重定向指令获取。

公开(公告)号：US5233702A

公开(公告)日：1993-08-03

申请号：US390587

申请日：1989-08-07

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Thomas R. Puzak ,  Rudolph N. Rechtschaffen

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Thomas R. Puzak ,  Rudolph N. Rechtschaffen

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6024

摘要： A cache memory system develops an optimum sequence for transferring data values between a main memory and a line buffer internal to the cache. At the end of a line transfer, the data in the line buffer is written into the cache memory as a block. Following an initial cache miss, the cache memory system monitors the sequence of data requests received for data in the line that is being read in from main memory. If the sequence being used to read in the data causes the processor to wait for a specific data value in the line, a new sequence is generated in which the specific data value is read at an earlier time in the transfer cycle. This sequence is associated with the instruction that caused the first miss and is used for subsequent misses caused by the instruction. If, in the process of handling a first miss related to a specific instruction, a second miss occurs which is caused by the same instruction but which is for data in a different line of memory, the sequence associated with the instruction is marked as an ephemeral miss. Data transferred to the line buffer in response to an ephemeral miss is not stored in the cache memory and limited to that portion of the line accessed within the line buffer.

公开(公告)号：US5210831A

公开(公告)日：1993-05-11

申请号：US429922

申请日：1989-10-30

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F9/38

CPC分类号： G06F9/3844

摘要： Methods and apparatus are described for processing branch instructions using a history based branch prediction mechanism (such as a branch history table) in combination with a data dependent branch table (DDBT), where the branch instructions can vary in both outcome and test operand location. The novel methods and apparatus are sensitive to branch mispredictions and to operand addresses used by the DDBT, to identify irrelevant DDBT entries. Irrelevant DDBT entries are identified within the prediction mechanism using state bits which, when set, indicate that: (1) a given entry in the prediction mechanism was updated by the DDBT and (2) subsequent to such update a misprediction occurred making further DDBT updates irrelevant. Once a DDBT entry is determined to be irrelevant, it is prevented from updating the prediction mechanism. The invention also provides methods and apparatus for locating and removing irrelevant entries from the DDBT. The update packet, sent by the DDBT to the history based prediction mechanism, is expanded to include the test operand address actually used by the DDBT. If the state bits indicate the update is irrelevant, then the operand address can be used to locate and delete the offending DDBT entry since the DDBT is organized based on operand addresses. Additionally, the invention provides for inhibiting creation of further DDBT entries when a Branch Wrong Guess event occurs subsequent to a DDBT update to a given prediction mechanism entry.

公开(公告)号：US4991090A

公开(公告)日：1991-02-05

申请号：US51792

申请日：1987-05-18

申请人： Philip G. Emma ,  Joshua W. Knight, III ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

发明人： Philip G. Emma ,  Joshua W. Knight, III ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio

IPC分类号： G06F9/38 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/3834

摘要： Monitoring apparatus is provided to allow out-of-sequence fetching of operands while preserving the appearance of in-sequence fetching to the processor of a computer. The key elements include a stack (119) of N entries holding the addresses of the last M, where M is less than or equal to N, out-of-sequence fetches. A comparator (103) is provided for comparing addresses in the stack with a test address. This test address is supplied via an OR gate (107) as either store addresses or cross-invalidate addresses, the latter being for a multiprocessor system. The addresses in the stack that compare with the test address are set as invalid. In addition, all addresses in the stack are set as invalid on the occurrence of a cache miss or serializing instruction. Finally, a select and check entry function (113) associates an address in the stack with the instruction it represents and deletes the address from the stack when the instruction is handled in its proper sequence.

公开(公告)号：US08677613B2

公开(公告)日：2014-03-25

申请号：US12774223

申请日：2010-05-20

申请人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

发明人： Eren Kursun ,  Philip G. Emma ,  Jude A. Rivers

IPC分类号： H05K3/30

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.

摘要翻译： 异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。 该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。 主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成 元件具有相对于主体层和芯片的平滑表面。

公开(公告)号：US20130283067A1

公开(公告)日：2013-10-24

申请号：US13601450

申请日：2012-08-31

申请人： Philip G. Emma

发明人： Philip G. Emma

IPC分类号： G06F1/26

CPC分类号： H01L25/0657 ,  G06F1/263 ,  G06F1/3234 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a semiconductor device includes a first processor chip comprising one or more processors, a second processor chip comprising one or more processors, and a plurality of input/output ports. The first and second processor chips are connected in a stacked configuration and commonly share the plurality of input/output ports. Methods are also provided to selectively operate the semiconductor device in one of a plurality of operating modes to control power of the semiconductor device.

公开(公告)号：US20130283009A1

公开(公告)日：2013-10-24

申请号：US13452113

申请日：2012-04-20

申请人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

发明人： Alper Buyuktosunoglu ,  Philip G. Emma ,  Allan M. Hartstein ,  Michael B. Healy ,  Krishnan Kunjunny Kailas

IPC分类号： G06F9/02

CPC分类号： G06F15/17387 ,  G06F9/3802

摘要： Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.

公开(公告)号：US20120268909A1

公开(公告)日：2012-10-25

申请号：US13535660

申请日：2012-06-28

申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

IPC分类号： H05K7/02

CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

摘要： A three-dimensional computer processing chip stack that includes a host layer disposed on at least one other layer in the stack. The host layer includes cavities formed thereon for receiving chips pre-configured with heterogeneous properties relative to each other. The cavities are formed to accommodate the heterogeneous properties of the chips. The chips are joined to respective surfaces of the cavities, thereby forming an element having a smooth surface with respect to the host layer and the chips.

摘要翻译： 一种三维计算机处理芯片堆叠，其包括布置在堆叠中的至少一个其他层上的主机层。 主体层包括形成在其上的空腔，用于接收预先配置有相对于彼此的异质特性的芯片。 形成空腔以适应芯片的不均匀性质。 芯片被连接到空腔的相应表面，从而形成相对于主体层和芯片具有平滑表面的元件。

公开(公告)号：US20110271141A1

公开(公告)日：2011-11-03

申请号：US12771293

申请日：2010-04-30

申请人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

发明人： Eren Kursun ,  Philip G. Emma ,  Stephen M. Gates

IPC分类号： G06F11/16 ,  G06F11/00

CPC分类号： G06F11/008 ,  G06F11/0724 ,  G06F11/0787 ,  G06F11/0793

摘要： Mechanisms are provided for use with a microprocessor chip, for storing selected reliability information in an on-chip non-volatile storage device. An on-chip reliability controller coupled to one or more on-chip resources of the microprocessor chip, collects raw reliability information from the one or more on-chip resources of the microprocessor chip. The on-chip reliability controller analyzes the raw reliability information to identify selected reliability information for the one or more resources of the microprocessor chip. The on-chip reliability controller stores the selected reliability information in the on-chip non-volatile storage device. The on-chip non-volatile storage device stores the selected reliability information even in the event of an overall failure of the microprocessor chip in which the microprocessor chip loses power. The on-chip non-volatile storage device has an interface through which the selected reliability information is accessible by an off-chip device even in the event of an overall failure of the microprocessor chip.

摘要翻译： 提供了与微处理器芯片一起使用的机制，用于将选定的可靠性信息存储在片上非易失性存储设备中。 耦合到微处理器芯片的一个或多个片上资源的片上可靠性控制器从微处理器芯片的一个或多个片上资源收集原始可靠性信息。 片上可靠性控制器分析原始可靠性信息，以识别微处理器芯片的一个或多个资源的选定可靠性信息。 片上可靠性控制器将所选择的可靠性信息存储在片上非易失性存储装置中。 即使在微处理器芯片失去电力的微处理器芯片的整体故障的情况下，片上非易失性存储设备也存储所选择的可靠性信息。 片上非易失性存储设备具有接口，即使在微处理器芯片的整体故障的情况下，所选择的可靠性信息也可通过片外设备访问。