公开(公告)号：US08097525B2

公开(公告)日：2012-01-17

申请号：US12201580

申请日：2008-08-29

申请人： John E. Barth, Jr. ,  Kerry Bernstein

发明人： John E. Barth, Jr. ,  Kerry Bernstein

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.

摘要翻译： 半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。 穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

公开(公告)号：US08013342B2

公开(公告)日：2011-09-06

申请号：US11939612

申请日：2007-11-14

申请人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Stephen Ellinwood Luce ,  Anthony Kendall Stamper

IPC分类号： H01L29/04

CPC分类号： G06F17/5077 ,  H01L21/6835 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/481 ,  H01L23/535 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/045 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01007 ,  H01L2924/01022 ,  H01L2924/00

摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

摘要翻译： 双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。 该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。 然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。 下晶片可以包括布线​​水平。 下部晶片可以包括用于触点的着陆焊盘。 与下晶片的硅层的接触可以被硅化。

公开(公告)号：US07960245B2

公开(公告)日：2011-06-14

申请号：US12029575

申请日：2008-02-12

申请人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Paul David Kartschoke ,  Anthony Kendall Stamper

IPC分类号： H01L21/30

CPC分类号： H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

公开(公告)号：US07882334B2

公开(公告)日：2011-02-01

申请号：US11276236

申请日：2006-02-20

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F15/76 ,  G06F1/00

CPC分类号： G06F9/3869 ,  G11C27/026

摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

摘要翻译： 公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

公开(公告)号：US07859878B2

公开(公告)日：2010-12-28

申请号：US12110375

申请日：2008-04-28

申请人： Igor Arsovski ,  Kerry Bernstein

发明人： Igor Arsovski ,  Kerry Bernstein

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A design structure embodied in a machine readable medium used in a design process includes a content addressable memory (CAM) device having an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括内容可寻址存储器（CAM）装置，其具有排列成字线方向的存储单元阵列和排列在位线方向上的列，并且配置有比较电路 将存储在阵列中的数据与存储在阵列的每一行和列中的数据进行比较，同时在阵列的每一行和列上指示匹配结果，从而产生二维的基于矩阵的数据比较操作。

公开(公告)号：US20100203689A1

公开(公告)日：2010-08-12

申请号：US12762427

申请日：2010-04-19

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

公开(公告)号：US20100052108A1

公开(公告)日：2010-03-04

申请号：US12201580

申请日：2008-08-29

申请人： John E. Barth, JR. ,  Kerry Bernstein

发明人： John E. Barth, JR. ,  Kerry Bernstein

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.

摘要翻译： 半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。 穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

公开(公告)号：US20100052100A1

公开(公告)日：2010-03-04

申请号：US12201462

申请日：2008-08-29

申请人： John E. Barth, JR. ,  Kerry Bernstein

发明人： John E. Barth, JR. ,  Kerry Bernstein

IPC分类号： H01L29/8605 ,  H01L21/02

CPC分类号： H01L29/861 ,  H01L21/761 ,  H01L21/76264 ,  H01L23/535 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.

摘要翻译： 公开了半导体结构。 半导体结构包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层 设置在掩埋绝缘体层正下方并形成导电路径的第二极性类型的带区域，设置在本体衬底中并与带区接触的第二极性类型的阱区，填充有导电的深沟槽 设置在阱区内的第一极性类型的材料以及由深沟槽的下部和阱区之间的接合部限定的静电放电（ESD）保护二极管。

公开(公告)号：US20090141527A1

公开(公告)日：2009-06-04

申请号：US11949063

申请日：2007-12-03

申请人： Igor Arsovski ,  Kerry Bernstein

发明人： Igor Arsovski ,  Kerry Bernstein

IPC分类号： G11C15/04

CPC分类号： G11C15/04

摘要： A content addressable memory (CAM) device includes an array of memory cells arranged in rows in a word line direction and columns arranged in a bit line direction, and compare circuitry configured to compare data presented to the array with data stored in each row and column of the array, and simultaneously indicate match results on each row and column of the array, thereby resulting in a two-dimensional, matrix-based data comparison operation.

摘要翻译： 一种内容可寻址存储器（CAM）装置，包括排列成字线方向的存储单元阵列和排列在位线方向上的列，以及比较电路，被配置为将呈现给阵列的数据与存储在每行和列中的数据进行比较 并且同时指示阵列的每一行和列上的匹配结果，从而导致二维的基于矩阵的数据比较操作。

公开(公告)号：US20090085152A1

公开(公告)日：2009-04-02

申请号：US11865079

申请日：2007-10-01

申请人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

发明人： Kerry Bernstein ,  Timothy J. Dalton ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Stephen E. Luce ,  Anthony K. Stamper

IPC分类号： H01L23/62 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto.

摘要翻译： 本文提供三维垂直电子熔丝结构及其制造方法。 形成熔丝结构的方法包括提供包括绝缘体层并在绝缘体层中形成开口的衬底。 该方法还包括沿着开口的侧壁形成导电层并用绝缘体材料填充开口。 垂直e熔丝结构包括第一接触层和第二接触层。 该结构还包括衬里在通孔内并与第一接触层和第二接触层电接触的导电材料。 当施加电流时，导电材料具有增加的电阻。