ARRAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME
    42.
    发明申请
    ARRAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME 审中-公开
    阵列基板和显示面板

    公开(公告)号:US20090109384A1

    公开(公告)日:2009-04-30

    申请号:US12138929

    申请日:2008-06-13

    IPC分类号: G02F1/1335

    摘要: An array substrate includes: a gate line, a data line crossing disposed substantially perpendicular to the gate line, a first switching element being electrically connected to the gate line and the data line, a pixel electrode being electrically connected to the first switching element to be formed in a pixel area, the pixel electrode having including an opening pattern, and a light-blocking wiring formed disposed in correspondence with the opening pattern is formed, the light-blocking wiring including a convex-concave pattern.

    摘要翻译: 阵列基板包括:栅极线,与栅极线大致垂直的数据线交叉,与栅极线和数据线电连接的第一开关元件,与第一开关元件电连接的像素电极, 形成在像素区域中,形成具有开口图案的像素电极和与开口图案对应地形成的遮光布线,所述遮光布线包括凸凹图案。

    Semiconductor memory device and method for operating the same
    43.
    发明申请
    Semiconductor memory device and method for operating the same 失效
    半导体存储器件及其操作方法

    公开(公告)号:US20080002485A1

    公开(公告)日:2008-01-03

    申请号:US11714155

    申请日:2007-03-06

    申请人: Kwang-Hyun Kim

    发明人: Kwang-Hyun Kim

    IPC分类号: G11C7/00

    摘要: A semiconductor memory device reduces power consumption during a refresh operation. The semiconductor memory device comprises a voltage generator, a sensing controller, an output driver and a data transmitter. The voltage generator is configured to generate an internal power voltage, which is lower during a power saving mode than during a normal mode, for a peripheral area. The sensing controller is configured to generate a control signal corresponding to a level of the internal power voltage. The output driver is configured to drive a transmitting data by using an output voltage. The data transmitter is configured to convert an inputting data into the transmitting data by using the internal power voltage or convert the inputting data into the transmitting data by using the output voltage in response to the control signal.

    摘要翻译: 半导体存储器件在刷新操作期间降低功耗。 半导体存储器件包括电压发生器,感测控制器,输出驱动器和数据发射器。 电压发生器被配置为在周边区域产生在省电模式期间比在正常模式期间更低的内部电力电压。 感测控制器被配置为产生对应于内部电源电压的电平的控制信号。 输出驱动器配置为通过使用输出电压来驱动发送数据。 数据发送器被配置为通过使用内部电源电压将输入数据转换成发送数据,或者通过响应于控制信号使用输出电压将输入数据转换成发送数据。

    Redundancy program circuit and methods thereof
    44.
    发明授权
    Redundancy program circuit and methods thereof 有权
    冗余编程电路及其方法

    公开(公告)号:US07307910B2

    公开(公告)日:2007-12-11

    申请号:US11169831

    申请日:2005-06-30

    IPC分类号: G11C17/18

    摘要: A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

    摘要翻译: 一种冗余程序电路及其方法。 冗余程序电路可以包括具有主熔丝的主熔丝电路,其输出用于指示主熔丝运行状态的操作使能信号,至少一个控制熔丝电路,包括至少一个控制熔丝,所述至少一个控制熔丝电路输出操作 用于所述至少一个控制熔丝的状态信号和被配置为基于所述操作状态信号和所述操作使能信号中的至少一个来复用解码地址信号位的复用单元。

    Boosted voltage generator with controlled pumping ratios
    45.
    发明申请
    Boosted voltage generator with controlled pumping ratios 审中-公开
    升压电压发生器,具有受控的泵送比

    公开(公告)号:US20070030052A1

    公开(公告)日:2007-02-08

    申请号:US11481725

    申请日:2006-07-06

    申请人: Kwang-Hyun Kim

    发明人: Kwang-Hyun Kim

    IPC分类号: G05F1/10

    CPC分类号: H02M3/07

    摘要: A boosted voltage generator includes first and second pumping units and a pumping ratio controller. The first pumping unit is for pumping a first pumping ratio of charge at an output node in response to a first signal, and the second pumping unit is for pumping a second pumping ratio of charge at the output node in response to a second signal. The pumping ratio controller is for setting the first and second pumping ratios.

    摘要翻译: 升压电压发生器包括第一和第二泵送单元和泵送比率控制器。 第一泵送单元用于响应于第一信号在输出节点处泵送电荷的第一泵浦比,并且第二泵送单元用于响应于第二信号泵送输出节点处的电荷的第二泵浦比。 泵送比控制器用于设定第一和第二泵送比。

    Liquid crystal display
    46.
    发明申请
    Liquid crystal display 审中-公开
    液晶显示器

    公开(公告)号:US20070008480A1

    公开(公告)日:2007-01-11

    申请号:US11482017

    申请日:2006-07-06

    IPC分类号: C09K19/02

    CPC分类号: G02F1/1396 G02F1/1362

    摘要: A liquid crystal display (LCD) includes a first electrode, a second electrode facing the first electrode, and a liquid crystal layer interposed between the first and second electrodes and having a twisted nematic alignment of liquid crystals, wherein rotation viscosity of the liquid crystal layer is 50 mPas-80 mPas, a cell gap, namely, the thickness of the liquid crystal layer, is 2.5 μm-5.0 μm, a voltage difference between the first and second electrodes is 0.2V-8.0V, and a response time can be obtained from the expression 6.78+(rotation viscosity)×0.81+(cell gap)×0.7+(rotation viscosity)×(cell gap)×0.14. The liquid crystal display having the twisted nematic alignment of liquid crystals, has the pitch of the liquid crystal layer within the range of 10 μm to 70 μm, a cell gap, namely, the thickness of the liquid crystal layer, within the range of 3.0 μm to 4.5 μm, and a voltage difference between the first and second electrodes within the range of 0.2V to 6.0V.

    摘要翻译: 液晶显示器(LCD)包括第一电极,面对第一电极的第二电极和介于第一和第二电极之间并具有液晶的扭曲向列取向的液晶层,其中液晶层的旋转粘度 50mPas-80mPa·s,单元间隙即液晶层的厚度为2.5μm〜5.0μm,第一和第二电极之间的电压差为0.2V〜8.0V,响应时间为 由表达式6.78+(旋转粘度)x0.81 +(单元间隙)x0.7 +(旋转粘度)×(单元间隙)x0.14得到。 具有液晶的扭曲向列取向的液晶显示器,液晶层的间距在10μm至70μm的范围内,单元格间隙即液晶层的厚度在3.0的范围内 至4.5微米,第一和第二电极之间的电压差在0.2V至6.0V的范围内。

    Semiconductor memory device and voltage level control method thereof

    公开(公告)号:US06535447B2

    公开(公告)日:2003-03-18

    申请号:US10000178

    申请日:2001-11-30

    IPC分类号: G11C700

    CPC分类号: G05F3/242

    摘要: The present invention discloses a semiconductor memory device and a voltage level control method thereof. The semiconductor memory device comprises multiple sub high voltage generators, multiple control circuits, a high voltage level detecting circuit, and a mode setting circuit. The multiple sub high voltage generators boost the high voltage level. The multiple control circuits control operations of each of the corresponding multiple sub high voltage generators responsive to each of corresponding high voltage detecting signals and to each of corresponding multiple control signals in the test mode. The high voltage level detecting circuit enabled by an active signal, detects the level drop of a high voltage and generates the high voltage detecting signal. The mode setting circuit sets the state of the multiple control signals responsive to the signals from the out side in the test mode. Performing the test by regulating the number of the multiple sub high voltage generators can prevent the semiconductor memory device from over kill. In addition, the test of the package state can be performed by enabling a few of the voltage generators than necessary for the full operation of the test mode.