公开(公告)号：US07961121B2

公开(公告)日：2011-06-14

申请号：US12824156

申请日：2010-06-26

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03M5/00

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US20100259426A1

公开(公告)日：2010-10-14

申请号：US12824156

申请日：2010-06-26

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03M5/00

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US20070206428A1

公开(公告)日：2007-09-06

申请号：US11612800

申请日：2006-12-19

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.

摘要翻译： 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

公开(公告)号：US07768429B2

公开(公告)日：2010-08-03

申请号：US12367134

申请日：2009-02-06

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03M5/00

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US20090146850A1

公开(公告)日：2009-06-11

申请号：US12367134

申请日：2009-02-06

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03M5/00

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US20070290902A1

公开(公告)日：2007-12-20

申请号：US11802886

申请日：2007-05-25

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Woo-Jin Lee

IPC分类号： H03M9/00

CPC分类号： H03K19/00346 ,  H04L25/03866 ,  H04L25/14 ,  H04L25/4908

摘要： Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

摘要翻译： 提供半导体器件，包括所述半导体器件的系统及其方法。 半导体器件的示例可以接收被调度用于发送的数据，对接收到的数据内的比特数进行加扰，按照给定的伪随机序列排列的加扰顺序。 所接收的数据可以是平衡的，使得等于第一逻辑电平的接收数据内的第一比特数与等于第二逻辑电平的接收数据中的第二比特数之间的差异低于阈值。 然后可以发送平衡和加扰的接收数据。 示例半导体器件可以以任何顺序执行加扰和平衡操作。 类似地，在接收端，另一个半导体器件可以通过对发送的数据进行解扰和不平衡来解码原始数据。 可以基于发送的数据被加扰和平衡的顺序以顺序执行解扰和不平衡操作。

公开(公告)号：US20070285121A1

公开(公告)日：2007-12-13

申请号：US11790014

申请日：2007-04-23

申请人： Kwang-II Park ,  Seung-Jun Bae ,  Seong-Jin Jang

发明人： Kwang-II Park ,  Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03K19/003

CPC分类号： H03K19/017545

摘要： A system including a plurality of transmission lines, a transmitter outputting respective signals to each of the plurality of transmission lines, a receiver receiving each of the plurality of signals via respective transmission lines, the receiver including a connection path connected to a termination voltage, a plurality of termination circuits distributed along the connection path, each termination circuit receiving a unique termination voltage from the connection path, receiving a respective signal and outputting a terminated input signal, a reference voltage generator including multiple reference voltage generator units connected to a common voltage, each reference voltage generator unit uniquely receiving at least one unique termination voltage and outputting a reference voltage, and a plurality of data input buffers receiving respective signals and an appropriate reference voltage of the multiple reference voltages output from the reference voltage generator.

摘要翻译： 一种包括多个传输线的系统，向多个传输线中的每一个输出相应信号的发射机，经由各个传输线接收多个信号中的每一个的接收机，所述接收机包括连接到终端电压的连接路径， 多个终端电路沿着连接路径分布，每个终端电路从连接路径接收唯一的终端电压，接收相应的信号并输出​​终止的输入信号;参考电压发生器，包括连接到公共电压的多个参考电压发生器单元， 每个参考电压发生器单元独特地接收至少一个唯一的终端电压并输出参考电压，以及多个数据输入缓冲器，其接收相应的信号和从参考电压发生器输出的多个参考电压的适当参考电压。

公开(公告)号：US20140019833A1

公开(公告)日：2014-01-16

申请号：US14031620

申请日：2013-09-19

申请人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

发明人： Seung-Jun Bae ,  Kwang-II Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

IPC分类号： G06F11/10

CPC分类号： G06F11/1004 ,  H03M13/09

摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

摘要翻译： 存储器系统包括存储器控制器和存储器件。 存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组 具有来自存储器控制器的命令/地址通过第三通道。

公开(公告)号：US08467255B2

公开(公告)日：2013-06-18

申请号：US13162948

申请日：2011-06-17

申请人： Dae-Hyun Kim ,  Seung-Jun Bae

发明人： Dae-Hyun Kim ,  Seung-Jun Bae

IPC分类号： G11C7/22

CPC分类号： G11C7/1012 ,  G11C7/1048 ,  G11C7/1084 ,  G11C7/1087

摘要： A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal

摘要翻译： 存储器件中的数据接收器包括积分单元，感测放大单元和锁存单元。 积分单元积分数据信号，以响应于采样反馈信号产生第一均衡信号。 数据信号包括顺序接收的多个数据。 感测放大单元响应于感测反馈信号感测第一均衡信号以产生第二均衡信号。 锁存单元锁存第二均衡信号以产生采样数据信号

公开(公告)号：US08199035B2

公开(公告)日：2012-06-12

申请号：US13069259

申请日：2011-03-22

申请人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

发明人： Seung-Jun Bae ,  Kwang-Chol Choe ,  Se-Won Seo

IPC分类号： H03M7/00

CPC分类号： H03M5/145

摘要： A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

摘要翻译： 数据通信设备或系统包括前同步码单元和数据接口。 前导码单元产生或检测具有第一数据线的第一长度的第一前同步码，并且生成或检测第二数据线具有第二长度的第二前同步码。 第一长度与第二长度不同，第一和第二数据线上的数据形成并行数据。 所述数据接口经由所述第一数据线与所述第一前同步码传送第一数据，并经由所述第二数据线与所述第二前同步码传送第二数据。 每个前导码的相应长度和/或相应模式是可调节的和/或可编程的。