公开(公告)号：US07259978B2

公开(公告)日：2007-08-21

申请号：US11221684

申请日：2005-09-08

申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。

公开(公告)号：US07242602B2

公开(公告)日：2007-07-10

申请号：US11002034

申请日：2004-12-02

申请人： Chang-Ho Lee ,  Jong-Hyun Choi

发明人： Chang-Ho Lee ,  Jong-Hyun Choi

IPC分类号： G11C5/08 ,  G11C5/06 ,  G11C11/12

CPC分类号： G11C11/4097 ,  G11C5/14 ,  G11C7/02 ,  Y10S257/907

摘要： A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend parallel to the memory device word lines, and can provide a power supply ground and/or signal line.

摘要翻译： 半导体存储器件包括间隔开的扭曲位线对，其相应的一个包括间隔开的扭曲区域。 导线与间隔开的扭绞线对的相应扭曲区域重叠。 导线可以平行于存储器件字线延伸，并且可以提供电源接地和/或信号线。

公开(公告)号：US20060176079A1

公开(公告)日：2006-08-10

申请号：US11348582

申请日：2006-02-06

申请人： Jong-Hyun Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Young-Hun Seo

IPC分类号： H03K19/0175

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/0005

摘要： An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.

摘要翻译： 一种用于半导体存储器件的输入/输出电路，包括数据输出电路，配置为响应于输入/输出使能信号缓冲半导体存储器件中的输出数据，以将缓冲的输出数据输出到输入/输出信号线， 数据输入电路，被配置为从输入/输出信号线接收输入数据并缓冲输入数据以将缓冲的输入数据传送到半导体存储器件;以及负载控制器，被配置为响应于控制输入/输出信号线上的负载 到输入/输出使能信号。

公开(公告)号：US06992943B2

公开(公告)日：2006-01-31

申请号：US10959804

申请日：2004-10-06

申请人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

发明人： Hyong-Ryol Hwang ,  Jong-Hyun Choi ,  Hyun-Soon Jang

IPC分类号： G11C7/00

CPC分类号： G11C11/40622 ,  G11C7/1018 ,  G11C11/406 ,  G11C11/4087

摘要： Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or 1/16) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

公开(公告)号：US20050122820A1

公开(公告)日：2005-06-09

申请号：US11005523

申请日：2004-12-06

申请人： Jong-Hyun Choi ,  Mi-Jo Kim ,  Kwang-Sook Noh ,  Beob-Rae Cho

发明人： Jong-Hyun Choi ,  Mi-Jo Kim ,  Kwang-Sook Noh ,  Beob-Rae Cho

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C7/20 ,  G11C11/4074

CPC分类号： G11C11/4074 ,  G11C5/143 ,  G11C7/20 ,  G11C2207/2227

摘要： A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.

摘要翻译： 半导体器件包括存储器和电源电压中断器，其被配置为响应于在存储器的DPD模式中产生的深度掉电（DPD）命令信号来中断施加到半导体器件的电路的外部电源电压。 电源电压移位器被配置为响应于DPD命令信号将电路中的电源电压移动到特定电平。

公开(公告)号：US06490222B2

公开(公告)日：2002-12-03

申请号：US09875371

申请日：2001-06-05

申请人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Jei-Hwan Yoo ,  Jae-Hoon Joo

发明人： Jong-Hyun Choi ,  Sang-Seok Kang ,  Jei-Hwan Yoo ,  Jae-Hoon Joo

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C8/14 ,  G11C29/34

摘要： A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.

摘要翻译： 本发明的半导体存储器件包括：主解码器，用于响应于第一解码信号，第一预充电信号和第二预充电信号产生字线使能信号; 响应于字线使能信号和第二解码信号的字线驱动信号的字线驱动器; 以及用于响应于命令信号产生第二预充电信号的电路。 响应于第一解码信号和第二预充电信号，字线驱动信号被顺序地去激活，以便减少地面噪声。

公开(公告)号：US06438042B1

公开(公告)日：2002-08-20

申请号：US09879076

申请日：2001-06-11

申请人： Sang-Seok Kang ,  Yun-Sang Lee ,  Jong-Hyun Choi ,  Jae-Hoon Joo

发明人： Sang-Seok Kang ,  Yun-Sang Lee ,  Jong-Hyun Choi ,  Jae-Hoon Joo

IPC分类号： G11C700

CPC分类号： G11C11/4094 ,  G11C7/12 ,  H01L27/10897

摘要： A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.

摘要翻译： 半导体存储器件包括第一和第二隔离晶体管，用于将一对位线与读出放大器电路电连接/隔离;以及MOS晶体管，其具有与第一和第二隔离晶体管的源极之一共享的源极区域。 MOS晶体管可以用作位线升压电容器。

公开(公告)号：US09966317B2

公开(公告)日：2018-05-08

申请号：US15298919

申请日：2016-10-20

申请人： Joung-Yeal Kim ,  Dae-Hyun Kwon ,  Mi-Young Woo ,  Joon-Sun Yoon ,  Jong-Hyun Choi

发明人： Joung-Yeal Kim ,  Dae-Hyun Kwon ,  Mi-Young Woo ,  Joon-Sun Yoon ,  Jong-Hyun Choi

IPC分类号： H01L21/66 ,  H01L23/498 ,  H01L49/02 ,  H01L27/08

CPC分类号： H01L22/32 ,  H01L23/49811 ,  H01L23/49838 ,  H01L27/0802 ,  H01L28/20

摘要： A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.

公开(公告)号：US09152251B2

公开(公告)日：2015-10-06

申请号：US13477204

申请日：2012-05-22

申请人： Guang-Hai Jin ,  Jae-Beom Choi ,  Kwan-Wook Jung ,  June-Woo Lee ,  Moo-Jin Kim ,  Jong-Hyun Choi

发明人： Guang-Hai Jin ,  Jae-Beom Choi ,  Kwan-Wook Jung ,  June-Woo Lee ,  Moo-Jin Kim ,  Jong-Hyun Choi

IPC分类号： G09G3/30 ,  G09G3/32 ,  G06F3/038

CPC分类号： G06F3/038 ,  G09G3/30 ,  G09G3/3266 ,  G09G2330/08

摘要： A scan driving circuit includes a shift register configured to sequentially output a first scan signal to scan lines through respective first output lines during a first section of a frame period, a simultaneous switching block configured to simultaneously output a second scan signal to the scan lines through respective second output lines during a second section of the frame period, the first and second periods of the frame period being different from each other, a switching device electrically connected to the second output line, and a repair line across the first output line and the second output line.

摘要翻译： 扫描驱动电路包括：移位寄存器，被配置为在帧周期的第一部分期间顺序地输出第一扫描信号以扫描线通过相应的第一输出线;同时切换块，被配置为同时向扫描线通过第二扫描信号 在帧周期的第二部分期间相应的第二输出线，帧周期的第一和第二周期彼此不同，电连接到第二输出线的开关装置和穿过第一输出线的修复线和 第二输出线。

公开(公告)号：US08822999B2

公开(公告)日：2014-09-02

申请号：US13313596

申请日：2011-12-07

申请人： Jong-Hyun Choi ,  Kwang-Hae Kim

发明人： Jong-Hyun Choi ,  Kwang-Hae Kim

IPC分类号： H01L33/42 ,  H01L33/16 ,  H01L33/08

CPC分类号： H01L27/3265 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/4908

摘要： An organic light-emitting display device includes a capacitor lower electrode that includes a semiconductor material doped with ion impurities. A first insulating layer covers an active layer and the capacitor lower electrode. A gate electrode includes a gate lower electrode formed of a transparent conductive material and a gate upper electrode formed of metal. A pixel electrode is electrically connected to the thin film transistor. A capacitor upper electrode is at the same level as the pixel electrode. An etch block layer is formed between the first insulating layer and the capacitor upper electrode. Source and drain electrodes are electrically connected to the active layer. A second insulating layer has an opening completely exposing the capacitor upper electrode. A third insulating layer exposes the pixel electrode. An intermediate layer includes an emissive layer. An opposite electrode faces the pixel electrode.

摘要翻译： 有机发光显示装置包括具有掺杂有离子杂质的半导体材料的电容器下电极。 第一绝缘层覆盖有源层和电容器下电极。 栅电极包括由透明导电材料形成的栅极下电极和由金属形成的栅极上电极。 像素电极电连接到薄膜晶体管。 电容器上电极与像素电极处于同一水平。 在第一绝缘层和电容器上电极之间形成蚀刻阻挡层。 源电极和漏电极电连接到有源层。 第二绝缘层具有完全暴露电容器上电极的开口。 第三绝缘层暴露像素电极。 中间层包括发射层。 相对电极面对像素电极。