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    Method and apparatus for minimizing skew between signals
    42.
    发明授权
    Method and apparatus for minimizing skew between signals 有权
    用于最小化信号之间的偏差的方法和装置

    公开(公告)号：US08779754B2

    公开(公告)日：2014-07-15

    申请号：US13019277

    申请日：2011-02-01

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    IPC分类号： H03K5/14 ,  H03K5/13 ,  H03K5/15

    CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

    摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

    摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

    Digital PVT compensation for delay chain
    43.
    发明授权
    Digital PVT compensation for delay chain 有权
    数字PVT补偿延时链

    公开(公告)号：US08680905B1

    公开(公告)日：2014-03-25

    申请号：US13486670

    申请日：2012-06-01

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/00

    CPC分类号： H03L7/00 ,  G11C7/04 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H03L7/0805 ,  H03L7/0812

    摘要： A circuit includes a delay locked loop (DLL), a calibration circuit and an output delay chain controlled by the calibration circuit. The DLL comprises a plurality of series-coupled first delay elements each of which has substantially the same first delay. The calibration circuit comprises a plurality of series-coupled second delay elements, each of which has substantially the same second delay that is less than the first delay, a first delay element, and a circuit for determining the minimum number of second delay elements that are needed to produce the first delay. The output delay chain comprises a plurality of series-coupled second delay elements, an input for receiving the input signal, and a circuit for selectively tapping the output delay chain at a plurality of taps in the output delay chain so as to produce in the input signal different delays of integral multiples of the second delay.

    摘要翻译： 电路包括由校准电路控制的延迟锁定环（DLL），校准电路和输出延迟链。 该DLL包括多个串联耦合的第一延迟元件，每个延迟元件具有基本上相同的第一延迟。 校准电路包括多个串联耦合的第二延迟元件，每个延迟元件具有基本相同的第二延迟小于第一延迟，第一延迟元件和用于确定第二延迟元件的最小数量的电路 需要产生第一个延迟。 输出延迟链包括多个串联耦合的第二延迟元件，用于接收输入信号的输入端和用于在输出延迟链中的多个抽头处有选择地分接输出延迟链的电路，以便产生输入 发出第二延迟的整数倍的不同延迟。

    Techniques for providing multiple delay paths in a delay circuit
    44.
    发明授权
    Techniques for providing multiple delay paths in a delay circuit 有权
    在延迟电路中提供多个延迟路径的技术

    公开(公告)号：US08159277B1

    公开(公告)日：2012-04-17

    申请号：US13031129

    申请日：2011-02-18

    申请人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    发明人： Pradeep Nagarajan ,  Yan Chong ,  Chiakang Sung ,  Joseph Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K2005/00058

    摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits includes variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit.

    摘要翻译： 反馈回路包括相位检测器和延迟电路。 相位检测器基于延迟周期信号产生输出信号。 延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。 每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。 延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。 每个延迟电路通过不同的延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。

    Multiple data rate interface architecture
    45.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US08098082B1

    公开(公告)日：2012-01-17

    申请号：US12954204

    申请日：2010-11-24

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    Method and apparatus for minimizing skew between signals
    46.
    发明授权
    Method and apparatus for minimizing skew between signals 有权
    用于最小化信号之间的偏差的方法和装置

    公开(公告)号：US07884619B1

    公开(公告)日：2011-02-08

    申请号：US12566157

    申请日：2009-09-24

    申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

    IPC分类号： G01R35/00 ,  G01R23/175 ,  G08B23/00 ,  H03L7/00

    CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

    摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

    摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

    Multiple data rate interface architecture
    47.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US07859304B1

    公开(公告)日：2010-12-28

    申请号：US12329553

    申请日：2008-12-06

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    Digitally controlled delay-locked loops
    48.
    发明授权
    Digitally controlled delay-locked loops 有权
    数字控制的延迟锁定环

    公开(公告)号：US07746134B1

    公开(公告)日：2010-06-29

    申请号：US11737116

    申请日：2007-04-18

    申请人： Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

    发明人： Sean Shau-Tu Lu ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  G11C7/22 ,  G11C7/222 ,  H03L7/091

    摘要： Digitally controlled delay-locked loops can have a phase detector, control logic, and a delay chain. The control logic generates digital signals in response to an output signal of the phase detector. The delay chain generates a delay that varies in response to the digital signals. In some embodiments, the control logic maintains logic states of the digital signals constant in response to an enable signal to maintain the delay of the delay chain constant in a lock mode of the digitally controlled delay-locked loop. In other embodiments, the delay of the delay chain varies by a discrete time period in response to a change in logic states of the digital signals, and the maximum phase error between a phase of the reference clock signal and a phase of the feedback clock signal is less than the discrete time period when the digitally controlled delay-locked loop is in a lock mode.

    摘要翻译： 数字控制的延迟锁定环路可以具有相位检测器，控制逻辑和延迟链。 控制逻辑响应于相位检测器的输出信号产生数字信号。 延迟链产生响应于数字信号而变化的延迟。 在一些实施例中，响应于使能信号，控制逻辑维持数字信号的逻辑状态恒定，以在数字控制的延迟锁定环的锁定模式中保持延迟链的延迟恒定。 在其他实施例中，延迟链的延迟响应于数字信号的逻辑状态的变化以及参考时钟信号的相位与反馈时钟信号的相位之间的最大相位误差而变化离散时间段 小于数字控制延迟锁定环处于锁定模式的离散时间周期。

    High-performance memory interface circuit architecture
    49.
    发明授权
    High-performance memory interface circuit architecture 有权
    高性能存储器接口电路架构

    公开(公告)号：US07227395B1

    公开(公告)日：2007-06-05

    申请号：US11055125

    申请日：2005-02-09

    申请人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    发明人： Joseph Huang ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Andy L. Lee ,  Brian D. Johnson

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0805

    摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

    摘要翻译： 可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。 然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略 相移控制设置，以产生精细的相移控制设置。 粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。