公开(公告)号：US20090240875A1

公开(公告)日：2009-09-24

申请号：US12050340

申请日：2008-03-18

申请人： Albert M. Chu ,  Paul C. Parries ,  Daryl M. Seitzer

发明人： Albert M. Chu ,  Paul C. Parries ,  Daryl M. Seitzer

IPC分类号： G11C15/04 ,  G11C7/00

CPC分类号： G11C15/043 ,  G11C11/406

摘要： Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method.

摘要翻译： 公开了具有两个分立存储器件的存储器电路的实施例，其具有存储基本上相同的数据库的两个分立存储器阵列。 第一设备是适于执行需要读取功能（即，所有更新和刷新操作）的所有维护操作的常规存储器。 第二设备是仅适用于执行并行搜索和重写操作的基于DRAM的CAM设备。 第二设备的覆盖操作的性能与第一设备的维护操作的性能一起发生，使得两个设备中的相应存储器单元存储基本上相同的数据值。 由于存储器件中的数据库基本上相同，并且由于维护和并行搜索操作不由同一设备执行，所以可以不中断地执行并行搜索操作。 还公开了相关设计结构和方法的实施例。

公开(公告)号：US20090184356A1

公开(公告)日：2009-07-23

申请号：US12016312

申请日：2008-01-18

申请人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

发明人： MaryJane Brodsky ,  Kangguo Cheng ,  Herbert L. Ho ,  Paul C. Parries ,  Kevin R. Winstel

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/1087

摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.

摘要翻译： 深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。 顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。 然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。 离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。 节点电介质和沟槽填充材料沉积到深沟槽中。 掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

公开(公告)号：US20090174031A1

公开(公告)日：2009-07-09

申请号：US11969986

申请日：2008-01-07

申请人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

发明人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

IPC分类号： H01L29/92 ,  H01L21/28 ,  G06F17/50

CPC分类号： H01L29/66181 ,  G11C11/404 ,  H01L27/0805 ,  H01L27/10861

摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。

公开(公告)号：US20090173980A1

公开(公告)日：2009-07-09

申请号：US11969989

申请日：2008-01-07

申请人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Herbert L. Ho ,  Paul C. Parries

发明人： Kangguo Cheng ,  Johnathan E. Faltermeier ,  Herbert L. Ho ,  Paul C. Parries

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10891

摘要： A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.

摘要翻译： 存储单元具有存取晶体管和具有设置在深沟槽内的电极的电容器。 STI氧化物覆盖电极的至少一部分，衬垫覆盖电极的剩余部分。 衬垫可以是一层氧化物上的氮化物层。 一些STI可以覆盖衬垫的一部分。 在存储器阵列中，可以通过STI氧化物和衬垫从电极隔离通过字线。

公开(公告)号：US07193262B2

公开(公告)日：2007-03-20

申请号：US10905094

申请日：2004-12-15

申请人： Herbert L. Ho ,  John E. Barth, Jr. ,  Ramachandra Divakaruni ,  Wayne F. Ellis ,  Johnathan E. Faltermeier ,  Brent A. Anderson ,  Subramanian S. Iyer ,  Deok-Kee Kim ,  Randy W. Mann ,  Paul C. Parries

发明人： Herbert L. Ho ,  John E. Barth, Jr. ,  Ramachandra Divakaruni ,  Wayne F. Ellis ,  Johnathan E. Faltermeier ,  Brent A. Anderson ,  Subramanian S. Iyer ,  Deok-Kee Kim ,  Randy W. Mann ,  Paul C. Parries

IPC分类号： H01L29/94 ,  H01L29/00

CPC分类号： H01L27/0805 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

摘要翻译： 一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。 在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

公开(公告)号：US07023758B2

公开(公告)日：2006-04-04

申请号：US11205565

申请日：2005-08-17

申请人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

发明人： David R. Hanson ,  Gregory J Fredeman ,  John W. Golz ,  Hoki Kim ,  Paul C. Parries

IPC分类号： G11C7/00

CPC分类号： G11C5/143 ,  G11C8/08

摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

摘要翻译： 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线 司机。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：US06967885B2

公开(公告)日：2005-11-22

申请号：US10757846

申请日：2004-01-15

申请人： John E. Barth, Jr. ,  Toshiaki Kirihata ,  Paul C. Parries

发明人： John E. Barth, Jr. ,  Toshiaki Kirihata ,  Paul C. Parries

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C2207/104

摘要： A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

摘要翻译： 通过允许通过刷新存储体选择信号刷新存储器阵列，同时使能另一阵列中的存储器访问操作来实现并发刷新模式。 通过插入集成在每个阵列中的行地址计数器，可以大大简化刷新地址管理。 在优选实施例中，同时刷新多个存储器阵列的任何组合，同时实现存储器访问操作。 此并发模式还支持多银行操作。

公开(公告)号：US5453400A

公开(公告)日：1995-09-26

申请号：US6662

申请日：1993-01-19

申请人： John R. Abernathey ,  Randy W. Mann ,  Paul C. Parries ,  Julie A. Springer

发明人： John R. Abernathey ,  Randy W. Mann ,  Paul C. Parries ,  Julie A. Springer

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC分类号： H01L21/768 ,  H01L21/76895 ,  H01L23/53271 ,  H01L2924/0002

摘要： A method of forming interconnections of devices of integrated circuits, especially interconnecting spaced source/drain regions and/or gate regions, and the resulting structures are provided. An etch-stop material such as silicon dioxide is deposited over the entire substrate on which the devices are formed. A layer of silicon is deposited over etch-stop material, and the silicon is selectively etched to reveal the etch-stop material at the regions to be connected. The etch-stop material at those regions is then removed. Following this a high-conductivity material, which is either a refractory metal or a silicide formed from layers of silicon and a refractory metal, is formed on the substrate connecting the spaced regions.

摘要翻译： 提供了形成集成电路器件的互连的方法，特别是互连间隔开的源极/漏极区域和/或栅极区域以及所得到的结构。 诸如二氧化硅的蚀刻停止材料沉积在其上形成器件的整个衬底上。 一层硅沉积在蚀刻停止材料上，并且硅被选择性地蚀刻以在要连接的区域上露出蚀刻停止材料。 然后去除那些区域处的蚀刻停止材料。 此后，在连接间隔开的区域的基板上形成高导电性材料，其是由硅层和难熔金属形成的难熔金属或硅化物。

公开(公告)号：US20130320422A1

公开(公告)日：2013-12-05

申请号：US13484657

申请日：2012-05-31

申请人： Josephine B. Chang ,  Babar A. Khan ,  Paul C. Parries ,  Xinhui Wang

发明人： Josephine B. Chang ,  Babar A. Khan ,  Paul C. Parries ,  Xinhui Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10844 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10879 ,  H01L27/1207 ,  H01L27/1211

摘要： A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

公开(公告)号：US20130134491A1

公开(公告)日：2013-05-30

申请号：US13307874

申请日：2011-11-30

申请人： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L27/10829 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

摘要翻译： 一种形成沟槽结构的方法，其包括在至少沟槽的侧壁上形成含金属层，以及在所述沟槽内形成未掺杂的半导体填充材料。 未掺杂的半导体填充材料和含金属层通过第一蚀刻凹陷到沟槽内的第一深度。 然后将未掺杂的半导体填充材料凹入到沟槽内的第二深度，其大于具有第二蚀刻的第一深度。 第二蚀刻暴露了含金属层的至少一个侧壁部分。 沟槽填充有掺杂的半导体含有材料填充物，其中掺杂半导体材料填充物与含金属层的至少侧壁部分直接接触。