公开(公告)号：US20190108018A1

公开(公告)日：2019-04-11

申请号：US15726293

申请日：2017-10-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gregory Edvenson ,  David Hulton ,  Jeremy Chritz

IPC: G06F9/30 ,  G06F15/18

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.