公开(公告)号：US20120001262A1

公开(公告)日：2012-01-05

申请号：US12829664

申请日：2010-07-02

申请人： Huang Soon Kang ,  Han-Hsin Kuo ,  Chi-Ming Yang ,  Shwang-Ming Jeng ,  Chin-Hsiang Lin

发明人： Huang Soon Kang ,  Han-Hsin Kuo ,  Chi-Ming Yang ,  Shwang-Ming Jeng ,  Chin-Hsiang Lin

IPC分类号： H01L29/78 ,  B24B7/00 ,  H01L21/306

CPC分类号： H01L23/5386 ,  H01L21/02074 ,  H01L21/28079 ,  H01L21/67011 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

摘要翻译： 本公开提供了一种制造半导体器件的方法，通过这种方法制造的半导体器件和用于执行这种方法的化学机械抛光（CMP）工具。 在一个实施例中，制造半导体器件的方法包括在衬底上的电介质层的沟槽中提供包括金属导体的集成电路（IC）晶片，以及执行化学机械抛光（CMP）工艺以平坦化金属导体 和电介质层。 该方法还包括清洁平坦化的金属导体和电介质层以除去CMP工艺中的残留物，用醇漂洗清洁的金属导体和介电层，并在惰性气体环境中干燥漂洗的金属导体和电介质层。

公开(公告)号：US20100109098A1

公开(公告)日：2010-05-06

申请号：US12339990

申请日：2008-12-19

申请人： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Chin-Hsiang Lin

发明人： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Chin-Hsiang Lin

IPC分类号： H01L29/51 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/49 ,  H01L21/336

CPC分类号： H01L29/518 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02362 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513

摘要： A method of fabricating a gate of a semiconductor device is provided. In an embodiment, the method includes forming a gate dielectric layer on a semiconductor substrate. An interface layer is formed on the gate dielectric layer. In an embodiment, the gate dielectric layer includes HfO2 and the interface layer includes Hf—N. A work function metal layer may be formed on the interface layer. A device is also provided.

摘要翻译： 提供一种制造半导体器件的栅极的方法。 在一个实施例中，该方法包括在半导体衬底上形成栅极电介质层。 界面层形成在栅介质层上。 在一个实施例中，栅介质层包括HfO 2，界面层包括Hf-N。 可以在界面层上形成功函数金属层。 还提供了一种设备。

公开(公告)号：US10857649B2

公开(公告)日：2020-12-08

申请号：US13240856

申请日：2011-09-22

申请人： Bo-I Lee ,  Huang Soon Kang ,  Chi-Ming Yang ,  Chin-Hsiang Lin

发明人： Bo-I Lee ,  Huang Soon Kang ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC分类号： B24B37/32 ,  B24B9/06

摘要： The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a polishing head that is operable to perform a polishing process to a wafer. The apparatus includes a retaining ring that is rotatably coupled to the polishing head. The retaining ring is operable to secure the wafer to be polished. The apparatus includes a soft material component located within the retaining ring. The soft material component is softer than silicon. The soft material component is operable to grind a bevel region of the wafer during the polishing process. The apparatus includes a spray nozzle that is rotatably coupled to the polishing head. The spray nozzle is operable to dispense a cleaning solution to the bevel region of the wafer during the polishing process.

公开(公告)号：US08843860B2

公开(公告)日：2014-09-23

申请号：US13409517

申请日：2012-03-01

申请人： Chin-Ming Lin ,  Chia-hung Huang ,  Chi-Ming Yang ,  Chin-Hsiang Lin ,  Yung-Cheng Chen ,  Chih-Wei Lin

发明人： Chin-Ming Lin ,  Chia-hung Huang ,  Chi-Ming Yang ,  Chin-Hsiang Lin ,  Yung-Cheng Chen ,  Chih-Wei Lin

IPC分类号： G06F17/50 ,  G03F7/20

CPC分类号： G03F7/70433

摘要： A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout.

摘要翻译： 一种方法包括建立初始照片布局，其中多个照片布置在垂直排列的列和水平排列的行中以覆盖半导体晶片。 一排照片或一列照片中的至少一列相对于相邻的行或列发射位移，以建立与至少一个移位行中的拍摄中的初始镜头布局不同的至少一个附加镜头布局，或 一列照片不与在初始镜头布局中对齐的相邻行或照片列中的镜头对齐。 选择初始镜头布局和至少一个附加镜头布局之一作为最终镜头布局。 使用最终镜头布局将晶片曝光。

公开(公告)号：US08664622B2

公开(公告)日：2014-03-04

申请号：US13443994

申请日：2012-04-11

申请人： Chih-Hong Hwang ,  Chun-Lin Chang ,  Chi-Ming Yang ,  Chin-Hsiang Lin ,  Wen-Yu Ku

发明人： Chih-Hong Hwang ,  Chun-Lin Chang ,  Chi-Ming Yang ,  Chin-Hsiang Lin ,  Wen-Yu Ku

IPC分类号： H01J27/00 ,  A61N5/00 ,  G21G5/00

CPC分类号： C23C14/48 ,  H01J27/08 ,  H01J37/08 ,  H01J2237/082 ,  H01J2237/31701

摘要： An apparatus comprises an ionization chamber for providing ions during a process of ion implantation, and an electron beam source device inside the ionization chamber. The electron beam source device comprises a field emission array having a plurality of emitters for generating electrons in vacuum under an electric field.

摘要翻译： 一种装置包括用于在离子注入过程中提供离子的电离室和电离室内的电子束源装置。 电子束源装置包括具有多个用于在电场下在真空中产生电子的发射器的场致发射阵列。

公开(公告)号：US08237231B2

公开(公告)日：2012-08-07

申请号：US13327992

申请日：2011-12-16

申请人： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

发明人： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC分类号： H01L27/088

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer.

摘要翻译： 具有金属栅极结构的半导体结构包括具有第一栅极的第一型场效应晶体管，包括：基板上的高k电介质材料，高k电介质材料层上的第一金属层，具有第一功函数，以及 在第一金属层上的第一铝层。 第一铝层包括包含铝，氮和氧的界面层。 该器件还包括具有第二栅极的第二类场效应晶体管，其包括：衬底上的高k电介质材料，高k电介质材料层上的第二金属层，具有不同于第一功函数的第二功函数， 和在第二金属层上的第二铝层。

公开(公告)号：US08119473B2

公开(公告)日：2012-02-21

申请号：US12651017

申请日：2009-12-31

申请人： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

发明人： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC分类号： H01L21/8232

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench.

摘要翻译： 本公开还提供了制造金属栅极叠层的方法的另一个实施例。 该方法包括在衬底上形成第一虚拟栅极和第二虚拟栅极; 从第一伪栅极去除多晶硅层，产生第一栅极沟槽; 在所述第一栅极沟槽中形成第一金属层和第一铝层; 对基材进行化学机械抛光（CMP）工艺; 使用含氮和氧的气体对所述第一铝层进行退火处理，在所述第一铝层上形成铝，氮和氧的界面层; 然后从第二伪栅极去除多晶硅层，产生第二栅极沟槽; 以及在所述第二栅极沟槽中的所述第二金属层上形成第二金属层和第二铝层。

公开(公告)号：US20110195570A1

公开(公告)日：2011-08-11

申请号：US12702525

申请日：2010-02-09

申请人： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

发明人： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC分类号： H01L21/3205

CPC分类号： H01L29/78 ,  C23C14/022 ,  C23C14/046 ,  C23C14/18 ,  C23C14/221 ,  C23C16/0263 ,  C23C16/045 ,  C23C16/06 ,  C23C16/48 ,  C23C16/484 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76877 ,  H01L29/4966 ,  H01L29/66545

摘要： The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios.

摘要翻译： 自下而上金属沉积以填充互连和替代栅极结构的方法的所述实施例使得能够在没有空隙的情况下间隙填充具有高纵横比的精细特征，并提供具有良好膜质量的金属膜。 通过气体簇离子束（GCIB）沉积的金属膜的原位预处理允许去除表面杂质和表面氧化物以改善下层与沉积的金属膜之间的粘附。 通过使用高能量的低频光源在较低温度下通过光致化学气相沉积（PI-CVD）沉积的金属膜表现出液体性质，这允许金属膜从下向上填充精细特征。 通过PI-CVD沉积的金属膜的后沉积退火致密化金属膜并从金属膜去除残余的气态物质。 对于先进的制造，这种自下而上的金属沉积方法解决了具有高纵横比的精细特征的间隙填充的挑战。

公开(公告)号：US20110156166A1

公开(公告)日：2011-06-30

申请号：US12651017

申请日：2009-12-31

申请人： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

发明人： Kuo Bin Huang ,  Ssu-Yi Li ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28247 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench.

摘要翻译： 本公开还提供了制造金属栅极叠层的方法的另一个实施例。 该方法包括在衬底上形成第一虚拟栅极和第二虚拟栅极; 从第一伪栅极去除多晶硅层，产生第一栅极沟槽; 在所述第一栅极沟槽中形成第一金属层和第一铝层; 对基材进行化学机械抛光（CMP）工艺; 使用含氮和氧的气体对所述第一铝层进行退火处理，在所述第一铝层上形成铝，氮和氧的界面层; 然后从第二虚拟栅极去除多晶硅层，产生第二栅极沟槽; 以及在所述第二栅极沟槽中的所述第二金属层上形成第二金属层和第二铝层。

公开(公告)号：US20100140716A1

公开(公告)日：2010-06-10

申请号：US12332057

申请日：2008-12-10

申请人： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

发明人： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28079 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/4958

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.

摘要翻译： 本发明提供集成电路。 集成电路包括具有第一区域和第二区域的半导体衬底; 在所述第一区域中的n型场效应晶体管（FET）的第一栅极堆叠; 以及第二区域中的p型FET的第二栅极堆叠。 第一栅极堆叠包括在半导体衬底上的高k电介质层，在高k电介质层上具有第一取向的第一晶体金属层和第一晶体金属层上的导电材料层。 第二栅极堆叠包括半导体衬底上的高k电介质层，在高k电介质层上具有第二取向的第二晶体金属层和第二晶体金属层上的导电材料层。