公开(公告)号：US20090146197A1

公开(公告)日：2009-06-11

申请号：US12143584

申请日：2008-06-20

申请人： Eun Soo Nam ,  Myoung Sook Oh ,  Ho Young Kim ,  Young Jun Chong ,  Hyun Kyu Yu

发明人： Eun Soo Nam ,  Myoung Sook Oh ,  Ho Young Kim ,  Young Jun Chong ,  Hyun Kyu Yu

IPC分类号： H01L31/00 ,  H01L21/00

CPC分类号： H01L27/14643 ,  G01S7/4863 ,  G01S17/89 ,  H01L27/14681 ,  H04N5/369

摘要： A photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal and a manufacturing method thereof are provided. According to the photo-detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate, so that it is possible to simplify manufacturing processes and to greatly increasing yield. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically speared from each other by using a polyimide. Therefore, a PN junction surface of the photodiode is buried, so that a surface leakage current can be reduced and an electrical reliability can be improved. In addition, a structure of the control devices can be simplified, so that image signal reception characteristics can be improved.

摘要翻译： 提供了与用于激光雷达图像信号单片集成的读出集成电路（ROIC）集成的光电检测器阵列装置及其制造方法。 根据光检测器阵列器件，在InP衬底上同时形成用于选择和输出激光雷达图像信号的光电二极管和控制装置，从而可以简化制造工艺并大大提高产量。 此外，在InP衬底上同时形成光电二极管和控制装置之后，通过使用聚酰亚胺将光电二极管和控制装置电分离。 因此，埋入光电二极管的PN结表面，从而能够减小表面泄漏电流，提高电气可靠性。 此外，可以简化控制装置的结构，从而可以提高图像信号接收特性。

公开(公告)号：US20090134944A1

公开(公告)日：2009-05-28

申请号：US12114705

申请日：2008-05-02

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H03B5/12

CPC分类号： H03B5/1231 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1253

摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.

摘要翻译： 提供电容变性双交叉耦合压控振荡器。 电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容 以增加主交叉振荡单元的负电阻。 因此，可以增加最大可获得的振荡频率并降低输入电容。

公开(公告)号：US07456063B2

公开(公告)日：2008-11-25

申请号：US11523212

申请日：2006-09-19

申请人： Sang Jin Byun ,  Hyun Kyu Yu

发明人： Sang Jin Byun ,  Hyun Kyu Yu

IPC分类号： H01L21/8242

CPC分类号： H01L27/0207

摘要： Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.

摘要翻译： 提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。 布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。 因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化 可以防止到去耦电容器的电源线。

公开(公告)号：US07391260B2

公开(公告)日：2008-06-24

申请号：US11510403

申请日：2006-08-25

申请人： Young Ho Kim ,  Mun Yang Park ,  Hyun Kyu Yu

发明人： Young Ho Kim ,  Mun Yang Park ,  Hyun Kyu Yu

IPC分类号： H03F1/36 ,  H03F3/45

CPC分类号： H03G1/007 ,  H03F1/08 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/381 ,  H03F2203/45138 ,  H03F2203/45522 ,  H03F2203/45524

摘要： An analog variable gain amplifier (VGA) adjusting a signal level of a mobile communication system is provided. More particularly, design of a VGA using an operational transconductance amplifier (OTA) having a wide linear input/output range is disclosed. The VGA includes two double-differential-pair OTAs and feedback resistors. A first differential input of a first double differential pair OTA receives an input signal from the forward stage, and a second differential input is negatively fed back through a differential output and a passive resistor. An input in which a first block of the connection structure and first and second differential inputs of a second double differential pair OTA are connected receives an output signal of the first block stage. The output is negatively fed back in series through a variable resistor whose resistance varies exponentially with an adjustment voltage from outside. According to the VGA, it is possible to provide a characteristic of linear variation of gain on a logarithmic scale with respect to a control voltage with a simple and inexpensive constitution. In addition, the VGA can be designed for a low pass filter having a conventional OTA used for a core circuit, and has a simple circuit structure. Therefore, the VGA is convenient for high integration and low-power design, and thus is appropriate for a terminal chip and so forth.

摘要翻译： 提供了调整移动通信系统的信号电平的模拟可变增益放大器（VGA）。 更具体地，公开了使用具有宽线性输入/输出范围的运算跨导放大器（OTA）的VGA的设计。 VGA包括两个双差分对OTA和反馈电阻。 第一双差分对OTA的第一差分输入接收来自前级的输入信号，并且第二差分输入通过差分输出和无源电阻负反馈。 其中连接结构的第一块和第二双差分对OTA的第一和第二差分输入相连接的输入端接收第一块级的输出信号。 输出通过可变电阻串联负反馈，其电阻随外部调整电压呈指数变化。 根据VGA，可以以简单且便宜的结构提供相对于控制电压的对数标度的增益的线性变化的特性。 此外，VGA可以设计用于具有用于核心电路的常规OTA的低通滤波器，并且具有简单的电路结构。 因此，VGA对于高集成度和低功耗设计是方便的，因此适用于终端芯片等。

公开(公告)号：US5840609A

公开(公告)日：1998-11-24

申请号：US951564

申请日：1997-10-16

申请人： Yeong Cheol Hyeon ,  Hyun Kyu Yu

发明人： Yeong Cheol Hyeon ,  Hyun Kyu Yu

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/336 ,  H01L29/49 ,  H01L21/26

CPC分类号： H01L29/6659 ,  H01L21/31051 ,  H01L29/4925 ,  H01L29/66545

摘要： A method for manufacturing a semiconductor device having a stacked gate electrode structure of self-aligned polysilicon-metal, which is capable of minimizing the variation in structural and electrical characteristics of the gate electrode, while utilizing the manufacturing process of forming a conventional silicone semiconductor memory device, is disclosed. According to the method for manufacturing a semiconductor device of the present invention, the conventional technique generally used in the manufacturing process of forming the silicon semiconductor device can be effectively utilized. Further, an excessive etch loss in the oxide layer can be restrained by using the oxide spacer of the self-aligned oxide layer in forming the metal layer at the gate electrode structure. Furthermore, it has an advantageous effect that the stable electrical characteristics of the resulting device can be obtained by using the polysilicon layer as a basic constituting material of the gate electrode thereof.

摘要翻译： 一种用于制造具有自对准多晶硅 - 金属堆叠栅电极结构的半导体器件的方法，其能够最小化栅电极的结构和电特性的变化，同时利用形成常规硅氧烷半导体存储器的制造工艺 设备。 根据本发明的半导体器件的制造方法，可以有效地利用通常用于形成硅半导体器件的制造工艺中的常规技术。 此外，通过在栅极电极结构形成金属层时，通过使用自对准氧化物层的氧化物间隔物，可以抑制氧化物层中的过度的蚀刻损失。 此外，通过使用多晶硅层作为其栅电极的基本构成材料，可以获得所得到的器件的稳定电特性。

公开(公告)号：US20120105116A1

公开(公告)日：2012-05-03

申请号：US13344513

申请日：2012-01-05

申请人： Byung Hun MIN ,  Hyun Kyu Yu

发明人： Byung Hun MIN ,  Hyun Kyu Yu

IPC分类号： H03L7/08

CPC分类号： H03L7/091 ,  H03L7/085 ,  H03L7/107 ,  H03L7/1075 ,  H03L7/183 ,  H03L2207/06 ,  H03L2207/50

摘要： There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

摘要翻译： 提供了一个频率合成器。 频率合成器包括：频率振荡器，其根据控制位调整输出频率; 具有预设的最小分频比的可编程分频器，所述编程分频器以可分分频比划分所述频率振荡器的输出频率; 接收可编程分频器的输出信号的计数器单元和参考频率，以在参考频率的一个周期期间对可编程分频器的输出信号的上升沿进行计数以产生计数值，并且当计数值 是1，并且当计数值为2时输出第二命中信号; 以及相位检测单元，输出通过从从计数值和参考频率获得的锁定相位的分数误差中减去可编程分频器的输出信号的分数误差而获得的控制位。

公开(公告)号：US20110148684A1

公开(公告)日：2011-06-23

申请号：US12970861

申请日：2010-12-16

申请人： Hyun Kyu Yu ,  Seon Ho Han ,  Young Hwa Kim ,  Seong Hwan Cho

发明人： Hyun Kyu Yu ,  Seon Ho Han ,  Young Hwa Kim ,  Seong Hwan Cho

IPC分类号： H03M1/38

CPC分类号： H03M1/46 ,  H03M1/827

摘要： There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.

摘要翻译： 提供了仅包括最小电容器以执行模数转换操作的逐次逼近模数转换器，从而使得可以具有非常强的工艺变化电阻特性，同时具有减小的电容和电路面积。 逐次逼近模数转换器可以包括提供参考电流的参考电流提供单元; 信号存储单元，存储通过对参考电流进行充电而产生的参考信号和从外部输入的输入信号; 比较单元，其比较所述参考信号和所述输入信号; 以及控制器，其基于所述比较单元的比较结果来控制所述参考电流供给单元，同时根据所述二进制码来改变提供给所述信号存储单元的参考电流的供给量。

公开(公告)号：US07933576B2

公开(公告)日：2011-04-26

申请号：US11946315

申请日：2007-11-28

申请人： Hong Gu Ji ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Hong Gu Ji ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H04B1/16

CPC分类号： H03D7/1425 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1475 ,  H03D2200/0043

摘要： A sub-harmonic mixer is provided, which includes: a mixer core having first and second transistors performing switching operations in response to a local oscillator (LO) signal and a radio frequency (RF) signal; a power source applying bias maximizing nonlinearity of a transistor included in the mixer core; an RF port applying an RF signal to the mixer core; an LO port applying an LO signal to the mixer core; and first and second phase delay circuits in which the RF signals applied to the first and second transistors have a 180-degree phase difference.

摘要翻译： 提供了一种亚谐波混频器，其包括：具有第一和第二晶体管的混频器核，其响应于本地振荡器（LO）信号和射频（RF）信号执行切换操作; 施加偏置最大化混合器核心中包括的晶体管的非线性的电源; 将RF信号施加到混频器核心的RF端口; LO端口将LO信号施加到混频器核心; 以及施加到第一和第二晶体管的RF信号具有180度相位差的第一和第二相位延迟电路。

公开(公告)号：US07852165B2

公开(公告)日：2010-12-14

申请号：US12114705

申请日：2008-05-02

申请人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

发明人： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC分类号： H03B5/12

CPC分类号： H03B5/1231 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1253

摘要： A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.

摘要翻译： 提供电容变性双交叉耦合压控振荡器。 电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容 以增加主交叉振荡单元的负电阻。 因此，可以增加最大可获得的振荡频率并降低输入电容。

公开(公告)号：US20100142648A1

公开(公告)日：2010-06-10

申请号：US12629018

申请日：2009-12-01

申请人： Hyun Kyu Yu ,  Mun Yang Park ,  Jae Hoon Shim

发明人： Hyun Kyu Yu ,  Mun Yang Park ,  Jae Hoon Shim

IPC分类号： H04L27/00

CPC分类号： H04L27/3863

摘要： There is provided an apparatus and method for In-phase/Quadrature-phase (I/Q) mismatch calibration. The apparatus includes: a symmetrical point extracting part receiving continuous wave signals and extracting an I/Q channel average locus of the continuous wave signals; an error extracting part extracting a degree of distortion of the continuous wave signals from the extracted I/Q channel average locus; and a calibrating part calibrating a mismatch between I-channel signals and Q-channel signals of the continuous wave signals using the degree of distortion of the continuous wave signals.

摘要翻译： 提供了用于同相/正交相（I / Q）不匹配校准的装置和方法。 该装置包括：对称点提取部分，接收连续波信号并提取连续波信号的I / Q信道平均轨迹; 从所提取的I / Q通道平均轨迹提取连续波信号的失真程度的误差提取部分; 以及使用连续波信号的失真程度来校准连续波信号的I信道信号和Q信道信号之间的失配的校准部分。