公开(公告)号：US20080182538A1

公开(公告)日：2008-07-31

申请号：US12056576

申请日：2008-03-27

申请人： Satoshi TANAKA ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

发明人： Satoshi TANAKA ,  Kazuo Watanabe ,  Masao Hotta ,  Toyohiko Hongo ,  Taizo Yamawaki ,  Masumi Kasahara ,  Kumiko Takikawa

IPC分类号： H04B1/06 ,  H04B1/10

CPC分类号： H04B1/30 ,  H03D2200/0047 ,  H03K21/16

摘要： A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

摘要翻译： 适合较大规模集成的收发器采用直接转换接收，以减少滤波器的数量。 此外，通过利用分频器来为RF频带提供具有本地振荡信号的接收机和发射机来减少VCO的数量。 每个具有固定分频比的分频器用于产生用于接收机的局部振荡信号，而具有可切换分频比的分频器用于产生用于发射机的本地振荡信号。 另外，用于基带信号的可变增益放大器设置有DC偏移电压检测器和DC偏移消除电路，用于支持高速数据通信以通过消除用于偏移的反馈回路内的滤波器的干涉来实现DC偏移的快速消除 消除。

公开(公告)号：US06996384B2

公开(公告)日：2006-02-07

申请号：US10455404

申请日：2003-06-06

申请人： Taizo Yamawaki ,  Satoshi Tanaka

发明人： Taizo Yamawaki ,  Satoshi Tanaka

IPC分类号： H04B1/18

CPC分类号： H04B1/406

摘要： Disclosed is a small-size receiver that exhibits high sensitivity when used with a plurality of frequencies or a plurality of radio communication systems. To provide a small-size, high-sensitivity, direct conversion receiver for use with a plurality of frequencies or a plurality of radio communication systems, the present invention has a high-frequency-input signal path for a low-noise amplifier optimized for use with various frequencies or radio communication systems. The high-frequency-input signal path includes at least one band-pass filter and its input and output matching circuits. A low-loss switching means is used to connect an optimum high-frequency-input signal path to the low-noise amplifier in accordance with a selected operation mode.

摘要翻译： 公开了当与多个频率一起使用时呈现高灵敏度的小尺寸接收机或多个无线电通信系统。 为了提供与多个频率或多个无线电通信系统一起使用的小尺寸，高灵敏度的直接转换接收机，本发明具有用于低噪声放大器的高频输入信号路径，其被优化用于 具有各种频率或无线电通信系统。 高频输入信号路径包括至少一个带通滤波器及其输入和输出匹配电路。 根据选择的操作模式，低损耗开关装置用于将最佳高频输入信号路径连接到低噪声放大器。

公开(公告)号：US20130049999A1

公开(公告)日：2013-02-28

申请号：US13338338

申请日：2011-12-28

申请人： TAKASHI OSHIMA ,  Taizo Yamawaki ,  Tomomi Takahashi

发明人： TAKASHI OSHIMA ,  Taizo Yamawaki ,  Tomomi Takahashi

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/804

摘要： A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

摘要翻译： 参考A / D转换单元并联连接到时间交织的A / D转换器的公共端作为校准对象，并且构成时间交织的A / D转换单元的每个单位A / D转换单元的输出， D转换器通过使用从参考A / D转换单元输出的低速高分辨率A / D转换结果在数字区域进行校准。 另外，fCLK / N（fCLK表示时间交织的A / D转换器的总体采样率，N是并行连接的单位A / D转换单元的数量的N相对于M）被设定为操作时钟频率 参考A / D转换单元。 所有单位A / D转换单元的采样可以与参考A / D转换单元的采样顺序同步，并且参考A / D转换器的工作时钟频率可以比总的采样率慢 时间交织的A / D转换器。

公开(公告)号：US08030995B2

公开(公告)日：2011-10-04

申请号：US12644833

申请日：2009-12-22

申请人： Yoichi Okubo ,  Manabu Nakamura ,  Junya Dosaka ,  Yasuhiro Takeda ,  Taizo Ito ,  Naoki Hongo ,  Taizo Yamawaki ,  Takashi Kawamoto ,  Akira Maeki

发明人： Yoichi Okubo ,  Manabu Nakamura ,  Junya Dosaka ,  Yasuhiro Takeda ,  Taizo Ito ,  Naoki Hongo ,  Taizo Yamawaki ,  Takashi Kawamoto ,  Akira Maeki

IPC分类号： H03G3/00

CPC分类号： H03F1/0227 ,  H03F3/19 ,  H03F2200/451 ,  H03F2200/462

摘要： A power circuit used for an amplifier, which includes an amplifier provided with a linear amplifier serving as a voltage source, a DC/DC converter serving as a current source, a hysteresis comparator controlling the DC/DC converter, and a current detector detecting output current from the linear amplifier to output the detected output current to the hysteresis comparator; and a switching restricting device for restricting a switching interval in the DC/DC converter such that the switching interval is not equal to or less than a constant time or is not shorter than the constant time.

摘要翻译： 用于放大器的电源电路，其包括放大器，该放大器设置有用作电压源的线性放大器，用作电流源的DC / DC转换器，控制DC / DC转换器的滞环比较器以及电流检测器检测输出 电流从线性放大器输出检测输出电流到滞后比较器; 以及用于限制DC / DC转换器中的切换间隔使得切换间隔不等于或小于恒定时间或不短于恒定时间的切换限制装置。

公开(公告)号：US20090017776A1

公开(公告)日：2009-01-15

申请号：US12169756

申请日：2008-07-09

申请人： TAKASHI OSHIMA ,  Taizo Yamawaki

发明人： TAKASHI OSHIMA ,  Taizo Yamawaki

IPC分类号： H04B1/38 ,  H04B17/00

CPC分类号： H04B1/0039

摘要： Conventional digital calibration type analog-to-digital converters cannot converge calibration within an preamble period of a packet signal. An analog-to-digital converter is subjected to digital calibration using a beacon signal, a polling signal, or another user signal or a signal applied from a transceiver side to a receiver side. Some or all of circuits are brought into a sleep mode in a period except data reception and the analog-to-digital converter calibration such that a signal monitor unit detects another signal to activate the circuit in the sleep mode for performing the calibration of the analog-to-digital converter for reducing the power consumption.

摘要翻译： 传统的数字校准型模数转换器不能在分组信号的前同步码周期内收敛校准。 使用信标信号，轮询信号或另一用户信号或从收发机侧向接收机侧施加的信号对模数转换器进行数字校准。 部分或全部电路在除了数据接收和模数转换器校准之外的周期中进入休眠模式，使得信号监视单元检测到另一个信号，以在休眠模式下激活电路，以执行模拟 数字转换器，用于降低功耗。

公开(公告)号：US20060084399A1

公开(公告)日：2006-04-20

申请号：US11246253

申请日：2005-10-11

申请人： Taizo Yamawaki ,  Yoshiaki Harasawa

发明人： Taizo Yamawaki ,  Yoshiaki Harasawa

IPC分类号： H04B1/04

CPC分类号： H04B1/1607 ,  H04B1/38

摘要： An object of the present invention is to provide a transmitter-receiver RF-IC having a built-in regulator, which can reduce a minimum value of an input voltage of the regulator without increasing its area, the input voltage being supplied from a battery, the transmitter-receiver RF-IC being capable of normal operation with the input voltage, whereby the operating time of a mobile terminal can be improved as compared with the prior art. According to the present invention, in order to achieve the above object, an output end of a regulator built into a RF-IC is first led to the outside of the RF-IC. Then, the output end is led to an area in proximity to the circuit block by use of wiring on a mobile terminal substrate whose resistance is low, or by use of wiring on a module whose resistance is low, thereby shortening the wiring length inside the RF-IC.

摘要翻译： 本发明的目的是提供一种具有内置调节器的发射器 - 接收器RF-IC，其可以减小调节器的输入电压的最小值而不增加其面积，从电池供应的输入电压， 发射机 - 接收机RF-IC能够利用输入电压进行正常操作，由此与现有技术相比可以提高移动终端的操作时间。 根据本发明，为了实现上述目的，首先将内置于RF-IC中的调节器的输出端引导到RF-IC的外部。 然后，通过使用电阻较低的移动终端基板上的布线，或者通过使用电阻较低的模块上的布线，将输出端导向靠近电路块的区域，从而缩短电路内部的布线长度 RF-IC。

公开(公告)号：US20060068726A1

公开(公告)日：2006-03-30

申请号：US11210734

申请日：2005-08-25

申请人： Taizo Yamawaki

发明人： Taizo Yamawaki

IPC分类号： H01Q11/12

CPC分类号： H03F1/32 ,  H03C1/06 ,  H03D3/007 ,  H03F1/0205 ,  H03F3/24 ,  H03F3/45286 ,  H03F2200/294 ,  H03F2203/45481 ,  H03F2203/45544 ,  H03F2203/45704 ,  H03G3/3047

摘要： A radio communication terminal is provided, in which the noise reduction and the cost reduction of a dual-mode transmitter handling two types of modulation systems of a non-constant amplitude modulation and a constant amplitude modulation can be realized. By applying a phase synchronization loop to the output signal of an orthogonal modulator and a synchronization loop to an envelope, a low-noise transmitter adapted to the constant amplitude modulation and the non-constant amplitude modulation is realized. Moreover, by preparing a variable gain amplifier for realizing the envelope modulation and a variable gain amplifier for realizing the output power control of a power amplifier, it becomes possible to use a general purpose PA with a fixed gain, and therefore, the cost reduction of the radio communication terminal can be achieved.

摘要翻译： 提供了一种无线电通信终端，其中可以实现处理非恒定幅度调制和恒定幅度调制的两种调制系统的双模式发射机的降噪和降低成本。 通过将相位同步环路应用于正交调制器的输出信号和向包络线的同步环路，实现了适用于恒定幅度调制和非恒定幅度调制的低噪声发射器。 此外，通过制备用于实现包络调制的可变增益放大器和用于实现功率放大器的输出功率控制的可变增益放大器，可以使用具有固定增益的通用PA，因此成本降低 可以实现无线通信终端。

公开(公告)号：US06970683B2

公开(公告)日：2005-11-29

申请号：US10375241

申请日：2003-02-28

申请人： Taizo Yamawaki ,  Takefumi Endo ,  Kazuo Watanabe ,  Kazuaki Hori ,  Julian Hildersley

发明人： Taizo Yamawaki ,  Takefumi Endo ,  Kazuo Watanabe ,  Kazuaki Hori ,  Julian Hildersley

IPC分类号： H03L7/10 ,  H03D13/00 ,  H03L7/00 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/16 ,  H03L7/18 ,  H04B1/3822 ,  H04B1/40 ,  H04L7/033

CPC分类号： H03L7/10 ,  H03D13/007 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/12 ,  H04B1/406

摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.

摘要翻译： 在PLL电路中，将LPF的数量减少到一个，以减少安装面积和引脚数量，并简化设计。 在一个实施例中，PLL电路包括可变增益相位比较器，混频器，LPF，VCO，耦合器以及控制VCO的开/关操作的控制电路。 可变增益相位比较器能够改变相位差增益。 VCO的操作的开/关由控制电路控制，使得VCO中的一个被关断。 相位差转换增益根据VCO的灵敏度而变化，因此PLL电路所需的LPF的数量可以减少到一个。

公开(公告)号：US06930549B2

公开(公告)日：2005-08-16

申请号：US10446859

申请日：2003-05-29

申请人： Hisayoshi Kajiwara ,  Kenji Toyota ,  Kazuhiko Hikasa ,  Taizo Yamawaki

发明人： Hisayoshi Kajiwara ,  Kenji Toyota ,  Kazuhiko Hikasa ,  Taizo Yamawaki

IPC分类号： H03G1/00 ,  H03G3/30 ,  H04B1/04 ,  H03F3/45

CPC分类号： H03G3/3042 ,  H03G1/0052

摘要： A variable gain amplifier of low amplitude distortion, and low noise, having a large variable range, is provided. A variable gain differential amplifier that controls a gain by use of bias current is used as each of unit amplifiers (VGAs) making up the variable gain amplifier. A large variable gain range is obtained by series-connecting a plurality of the variable gain differential amplifiers. An attenuator is installed on the input side of the unit amplifier (VGA) at least in the initial stage. By doing so, it becomes possible to prevent amplitude distortion from occurring to the respective VGAs. An attenuator utilizing voltage division by capacitors, generating no noise, is used for lowering noise. Further, the variable gain amplifier is provided with a fixed gain amplifier installed in the final stage as necessary in order to obtain a total gain as desired. With the use of the variable gain amplifier as a variable gain amplifier for output power control of a polar loop transmitter, an excellent function for output power control can be achieved without causing significant deterioration in distortion characteristic and noise characteristic thereof.

摘要翻译： 提供了具有较大可变范围的低振幅失真和低噪声的可变增益放大器。 使用通过使用偏置电流来控制增益的可变增益差分放大器被用作构成可变增益放大器的单位放大器（VGA）中的每一个。 通过串联连接多个可变增益差分放大器来获得大的可变增益范围。 至少在初始阶段，衰减器安装在单元放大器（VGA）的输入侧。 通过这样做，可以防止对各个VGA产生振幅失真。 使用由电容器分压而不产生噪声的衰减器用于降低噪声。 此外，可变增益放大器设置有必要时安装在最后级的固定增益放大器，以便根据需要获得总增益。 通过使用可变增益放大器作为用于极性环路发送器的输出功率控制的可变增益放大器，可以实现输出功率控制的优异功能，而不会引起失真特性和噪声特性的显着劣化。

公开(公告)号：US08411730B2

公开(公告)日：2013-04-02

申请号：US12955865

申请日：2010-11-29

申请人： Koji Maeda ,  Taizo Yamawaki ,  Yukinori Akamine

发明人： Koji Maeda ,  Taizo Yamawaki ,  Yukinori Akamine

IPC分类号： H04B1/38

CPC分类号： H04L27/3863 ,  H04B17/0085 ,  H04B17/21 ,  H04L25/06

摘要： The semiconductor integrated communication circuit includes:a low-noise amplifier; a receive mixer; a receive VCO; a demodulation-processing circuit; a modulation-processing circuit; a transmit mixer; a transmit VCO; a second-order-distortion-characteristic-calibration circuit; a quadrature-receive-signal-calibration circuit; and a test-signal generator. The test-signal generator generates first and second test signals using the transmit VCO. In the second-order-distortion-characteristic-calibration mode, the second-order-distortion-characteristic-calibration circuit variably changes an operation parameter of the receive mixer thereby to calibrate the second-order distortion characteristic to achieve its best condition while the first test signal is supplied to the receive mixer. In the quadrature-receive-signal-calibration mode, the quadrature-receive-signal-calibration circuit calibrates IQ mismatch of a quadrature receive signal to achieve the best condition thereof while the second test signal is supplied to the receive mixer. The integrated communication circuit can minimize the increase in chip footprint of a test-signal-generating circuit used to perform calibrations of both the second-order characteristic and IQ mismatch.

摘要翻译： 半导体集成通信电路包括：低噪声放大器; 接收混音器 接收VCO; 解调处理电路; 调制处理电路; 发射混频器; 发射VCO; 二阶畸变特征校准电路; 正交接收信号校准电路; 和测试信号发生器。 测试信号发生器使用发射VCO产生第一和第二测试信号。 在二次失真特性校准模式中，二阶失真特性校准电路可变地改变接收混频器的操作参数，从而校正二阶失真特性，以实现其最佳状态，而第一 测试信号被提供给接收混频器。 在正交接收信号校准模式中，正交接收信号校准电路校准正交接收信号的IQ失配，以实现其最佳状态，同时将第二测试信号提供给接收混频器。 集成通信电路可以最小化用于执行二阶特性和IQ失配校准的测试信号发生电路的芯片占用面积的增加。