摘要:
The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.
摘要:
There is provided a MOSFET structure and a method of fabricating the same. The method includes: providing a semiconductor substrate; forming a dummy gate on the semiconductor substrate; forming source/drain regions; selectively etching the dummy gate to a position where a channel is to be formed; and epitaxially growing a channel layer at the position where the channel is to be formed and forming a gate on the channel layer, wherein the channel layer comprises a material of high mobility. Thereby, the channel of the device is replaced with the material of high mobility after the source/drain region is formed, and thus it is possible to suppress the short channel effect and also to improve the device performance.
摘要:
The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: depositing an interlayer dielectric layer (105) on a semiconductor substrate (101) to cover a source/drain region (102) and a gate stack on the semiconductor substrate (101); etching the interlayer dielectric layer and the source/drain region, so as to form a contact hole (110) extending into the source/drain region; conformally forming an amorphous layer (111) on an exposed part of the source/drain region; forming a metal silicide layer (113) on a surface of the amorphous layer (111); and filling the contact hole (110) with a contact metal (114). Correspondingly, the present invention further provides a semiconductor structure. The present invention etches the source/drain region so that the exposed part comprises the bottom and a sidewall, thereby expanding the contact area between the contact metal in the contact hole and the source/drain region, and reducing the contact resistance. The present invention effectively eliminates EOR defects caused by the amorphous ion implantation by forming an amorphous substance by a selective deposition.
摘要:
The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed.
摘要:
The present application discloses a semiconductor device and a method of manufacturing the same. Wherein, the semiconductor device comprises: a semiconductor substrate; a stressor embedded in the semiconductor substrate; a channel region disposed on the stressor; a gate stack disposed on the channel region; a source/drain region disposed on two sides of the channel region and embedded in the semiconductor substrate; wherein, surfaces of the stressor comprise a top wall, a bottom wall, and side walls, the side walls comprising a first side wall and a second side wall, the first side wall connecting the top wall and the second side wall, the second side wall connecting the first side wall and the bottom wall, the angle between the first side wall and the second side wall being less than 180°, and the first sidewall and the second side wall being roughly symmetrical with respect to a plane parallel to the semiconductor substrate. Embodiments of the present invention are applicable to the stress engineering technology in the semiconductor device manufacturing.
摘要:
The present application provides a MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first buried insulating layer on the semiconductor substrate; a back gate formed in a first semiconductor layer which is on the first buried insulating layer; a second buried insulating layer on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is on the second buried insulating layer; a gate on the second semiconductor layer; and electrical contacts on the source/drain regions, the gate and the back gate, wherein the back gate is only under a channel region and one of the source/drain regions and not under the other of the source/drain regions, and a common electrical contact is formed between the back gate and the one of the source/drain regions. The MOSFET improves an effect of suppressing short channel effects by an asymmetric back gate, and reduces a footprint on a wafer by using the common conductive via.
摘要:
The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET is formed on an SOI wafer, comprising: a shallow trench isolation for defining an active region in the semiconductor layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; a channel region in the semiconductor layer and sandwiched by the source region and the drain region; a back gate in the semiconductor substrate; a first dummy gate stack overlapping with a boundary between the semiconductor layer and the shallow trench isolation; and a second dummy gate stack on the shallow trench isolation, wherein the MOSFET further comprises a plurality of conductive vias which are disposed between the gate stack and the first dummy gate stack and electrically connected to the source region and the drain region respectively, and between the first dummy gate stack and the second dummy gate stack and electrically connected to the back gate. The MOSFET avoids short circuit between the back gate and the source/drain regions by the dummy gate stacks.
摘要:
The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.
摘要:
A method of manufacturing a semiconductor device, wherein thermal annealing of the source/drain regions is performed before reverse Halo implantation to form a reverse Halo implantation region. The method comprises: removing the dummy gate to expose the gate dielectric layer, so as to form an opening; performing reverse Halo implantation on the substrate via the opening, so as to form a reverse Halo implantation region in the channel of the device; activating the dopants in the reverse Halo implantation region by annealing; and performing subsequent device processing. Deterioration of the gate stack due to the reverse Halo ions implantation may be avoided by the present invention, such that the reverse Halo ions implantation may be applied to the device with a metal gate stack, and the short channel effects may be alleviated and controlled, thereby the performance of the device is enhanced.
摘要:
The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming a dielectric film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin; and forming a retrograde doped well structure on the inner walls of the first semiconductor fin and the second semiconductor fin, wherein the inner walls thereof are opposite to each other. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, a retrograde doped well structure is formed on the sidewalls of the two semiconductor fins that are opposite to each other, so that the width of the source/drain depletion layer may be effectively reduced, and thereby the short channel effect is reduced.